testsuites/validation/tc-cache-no-disable-data.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RtemsCacheValCacheNoDisableData
0007  */
0008
0009 /*
0010  * Copyright (C) 2024 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 /*
0035  * This file is part of the RTEMS quality process and was automatically
0036  * generated.  If you find something that needs to be fixed or
0037  * worded better please post a report or patch to an RTEMS mailing list
0038  * or raise a bug report:
0039  *
0040  * https://www.rtems.org/bugs.html
0041  *
0042  * For information on updating and regenerating please refer to the How-To
0043  * section in the Software Requirements Engineering chapter of the
0044  * RTEMS Software Engineering manual.  The manual is provided as a part of
0045  * a release.  For development sources please refer to the online
0046  * documentation at:
0047  *
0048  * https://docs.rtems.org
0049  */
0050
0051 #ifdef HAVE_CONFIG_H
0052 #include "config.h"
0053 #endif
0054
0055 #include <rtems.h>
0056 #include <setjmp.h>
0057
0058 #include "tx-support.h"
0059
0060 #include <rtems/test.h>
0061
0062 /**
0063  * @defgroup RtemsCacheValCacheNoDisableData \
0064  *   spec:/rtems/cache/val/cache-no-disable-data
0065  *
0066  * @ingroup TestsuitesValidationCache
0067  *
0068  * @brief Tests some @ref RTEMSAPIClassicCache directives.
0069  *
0070  * This test case performs the following actions:
0071  *
0072  * - Call the rtems_cache_disable_data() directive.
0073  *
0074  *   - Check that the right fatal error occurred.
0075  *
0076  * - Call the rtems_cache_invalidate_entire_data() directive.
0077  *
0078  * - Call the rtems_cache_invalidate_entire_data() directive with maskable
0079  *   interrupts disabled.
0080  *
0081  * @{
0082  */
0083
0084 static jmp_buf fatal_before;
0085
0086 static Atomic_Uint fatal_counter;
0087
0088 static rtems_fatal_source fatal_source;
0089
0090 static rtems_fatal_code fatal_code;
0091
0092 static void FatalRecordAndJump(
0093   rtems_fatal_source source,
0094   rtems_fatal_code   code,
0095   void              *arg
0096 )
0097 {
0098   (void) arg;
0099
0100   fatal_source = source;
0101   fatal_code = code;
0102   _Atomic_Fetch_add_uint( &fatal_counter, 1, ATOMIC_ORDER_RELAXED );
0103   _ISR_Set_level( 0 );
0104   longjmp( fatal_before, 1 );
0105 }
0106
0107 /**
0108  * @brief Call the rtems_cache_disable_data() directive.
0109  */
0110 static void RtemsCacheValCacheNoDisableData_Action_0( void )
0111 {
0112   SetFatalHandler( FatalRecordAndJump, NULL );
0113
0114   if ( setjmp( fatal_before ) == 0 ) {
0115     rtems_cache_disable_data();
0116   }
0117
0118   SetFatalHandler( NULL, NULL );
0119
0120   /*
0121    * Check that the right fatal error occurred.
0122    */
0123   T_eq_uint(
0124     _Atomic_Load_uint( &fatal_counter, ATOMIC_ORDER_RELAXED ),
0125     1
0126   );
0127   T_eq_int( fatal_source, INTERNAL_ERROR_CORE );
0128   T_eq_ulong(
0129     fatal_code,
0130     INTERNAL_ERROR_CANNOT_DISABLE_DATA_CACHE
0131   );
0132 }
0133
0134 /**
0135  * @brief Call the rtems_cache_invalidate_entire_data() directive.
0136  */
0137 static void RtemsCacheValCacheNoDisableData_Action_1( void )
0138 {
0139   rtems_cache_invalidate_entire_data();
0140 }
0141
0142 /**
0143  * @brief Call the rtems_cache_invalidate_entire_data() directive with maskable
0144  *   interrupts disabled.
0145  */
0146 static void RtemsCacheValCacheNoDisableData_Action_2( void )
0147 {
0148   rtems_interrupt_level level;
0149
0150   rtems_interrupt_local_disable(level);
0151   rtems_cache_invalidate_entire_data();
0152   rtems_interrupt_local_enable(level);
0153 }
0154
0155 /**
0156  * @fn void T_case_body_RtemsCacheValCacheNoDisableData( void )
0157  */
0158 T_TEST_CASE( RtemsCacheValCacheNoDisableData )
0159 {
0160   RtemsCacheValCacheNoDisableData_Action_0();
0161   RtemsCacheValCacheNoDisableData_Action_1();
0162   RtemsCacheValCacheNoDisableData_Action_2();
0163 }
0164
0165 /** @} */