libtests/record01/init.c

0001 /*
0002  * SPDX-License-Identifier: BSD-2-Clause
0003  *
0004  * Copyright (C) 2018, 2019 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifdef HAVE_CONFIG_H
0029 #include "config.h"
0030 #endif
0031
0032 #include <rtems/record.h>
0033 #include <rtems/recordserver.h>
0034 #include <rtems.h>
0035
0036 #include <sys/endian.h>
0037 #include <sys/socket.h>
0038
0039 #include <string.h>
0040 #include <unistd.h>
0041
0042 #include <netinet/in.h>
0043
0044 #ifdef RTEMS_NETWORKING
0045 #include <rtems/rtems_bsdnet.h>
0046 #endif
0047
0048 #include <tmacros.h>
0049
0050 const char rtems_test_name[] = "RECORD 1";
0051
0052 #define ITEM_COUNT 4
0053
0054 #define ITEM_SIZE (ITEM_COUNT * sizeof(rtems_record_item))
0055
0056 typedef struct {
0057   Record_Control control;
0058   rtems_record_item items[ITEM_COUNT];
0059 } test_context;
0060
0061 static test_context test_instance;
0062
0063 const Record_Configuration _Record_Configuration = {
0064   .item_count = ITEM_COUNT
0065 };
0066
0067 #define UE(user) RTEMS_RECORD_USER(user)
0068
0069 #define TE(t, e) RTEMS_RECORD_TIME_EVENT(t, e)
0070
0071 static const rtems_record_item expected_items_0[ITEM_COUNT] = {
0072   { .event = TE(2, UE(1)), .data = 3 }
0073 };
0074
0075 static const rtems_record_item expected_items_1[ITEM_COUNT] = {
0076   { .event = TE(2, UE(1)), .data = 3 },
0077   { .event = TE(6, UE(5)), .data = 7 }
0078 };
0079
0080 static const rtems_record_item expected_items_2[ITEM_COUNT] = {
0081   { .event = TE(2, UE(1)), .data = 3 },
0082   { .event = TE(6, UE(5)), .data = 7 },
0083   { .event = TE(10, UE(9)), .data = 11 }
0084 };
0085
0086 static const rtems_record_item expected_items_3[ITEM_COUNT] = {
0087   { .event = TE(2, UE(1)), .data = 3 },
0088   { .event = TE(6, UE(5)), .data = 7 },
0089   { .event = TE(10, UE(9)), .data = 11 },
0090   { .event = TE(14, UE(13)), .data = 15 }
0091 };
0092
0093 static const rtems_record_item expected_items_4[ITEM_COUNT] = {
0094   { .event = TE(18, UE(17)), .data = 19 },
0095   { .event = TE(6, UE(5)), .data = 7 },
0096   { .event = TE(10, UE(9)), .data = 11 },
0097   { .event = TE(14, UE(13)), .data = 15 }
0098 };
0099
0100 static const rtems_record_item expected_items_5[ITEM_COUNT] = {
0101   { .event = TE(2, UE(1)), .data = 3 }
0102 };
0103
0104 static const rtems_record_item expected_items_6[ITEM_COUNT] = {
0105   { .event = TE(2, UE(1)), .data = 3 },
0106   { .event = TE(6, UE(5)), .data = 7 }
0107 };
0108
0109 static const rtems_record_item expected_items_7[ITEM_COUNT] = {
0110   { .event = TE(2, UE(1)), .data = 3 },
0111   { .event = TE(6, UE(5)), .data = 7 },
0112   { .event = TE(10, UE(9)), .data = 11 }
0113 };
0114
0115 #ifdef RTEMS_NETWORKING
0116 static const rtems_record_item expected_items_8[] = {
0117   { .event = TE(0, RTEMS_RECORD_PROCESSOR), .data = 0 },
0118   { .event = TE(0, RTEMS_RECORD_PER_CPU_TAIL), .data = 0 },
0119   { .event = TE(0, RTEMS_RECORD_PER_CPU_HEAD), .data = 3 },
0120   { .event = TE(2, UE(1)), .data = 3 },
0121   { .event = TE(5, UE(4)), .data = 6 },
0122   { .event = TE(8, UE(7)), .data = 9 }
0123 };
0124
0125 static const rtems_record_item expected_items_9[] = {
0126   { .event = TE(0, RTEMS_RECORD_PROCESSOR), .data = 0 },
0127   { .event = TE(0, RTEMS_RECORD_PER_CPU_TAIL), .data = 3 },
0128   { .event = TE(0, RTEMS_RECORD_PER_CPU_HEAD), .data = 5 },
0129   { .event = TE(11, UE(10)), .data = 12 },
0130   { .event = TE(14, UE(13)), .data = 15 }
0131 };
0132
0133 static const rtems_record_item expected_items_10[] = {
0134   { .event = TE(0, RTEMS_RECORD_PROCESSOR), .data = 0 },
0135   { .event = TE(0, RTEMS_RECORD_PER_CPU_TAIL), .data = 5 },
0136   { .event = TE(0, RTEMS_RECORD_PER_CPU_HEAD), .data = 8 },
0137   { .event = TE(17, UE(16)), .data = 18 },
0138   { .event = TE(20, UE(19)), .data = 21 },
0139   { .event = TE(23, UE(22)), .data = 24 }
0140 };
0141
0142 static const rtems_record_item expected_items_11[] = {
0143   { .event = TE(0, RTEMS_RECORD_PROCESSOR), .data = 0 },
0144   { .event = TE(0, RTEMS_RECORD_PER_CPU_TAIL), .data = 8 },
0145   { .event = TE(0, RTEMS_RECORD_PER_CPU_HEAD), .data = 9 },
0146   { .event = TE(26, UE(25)), .data = 27 }
0147 };
0148
0149 static const rtems_record_item expected_items_12[] = {
0150   { .event = TE(0, RTEMS_RECORD_PROCESSOR), .data = 0 },
0151   { .event = TE(0, RTEMS_RECORD_PER_CPU_TAIL), .data = 9 },
0152   { .event = TE(0, RTEMS_RECORD_PER_CPU_HEAD), .data = 15 },
0153   { .event = TE(38, UE(37)), .data = 39 },
0154   { .event = TE(41, UE(40)), .data = 42 },
0155   { .event = TE(44, UE(43)), .data = 45 }
0156 };
0157
0158 static const rtems_record_item expected_items_13[] = {
0159   { .event = TE(0, RTEMS_RECORD_THREAD_ID), .data = 0x9010001 },
0160   {
0161     .event = TE(0, RTEMS_RECORD_THREAD_NAME),
0162     .data = rtems_build_name('E', 'L', 'D', 'I')
0163   },
0164   { .event = TE(0, RTEMS_RECORD_THREAD_ID), .data = 0xa010001 },
0165   {
0166     .event = TE(0, RTEMS_RECORD_THREAD_NAME),
0167     .data = rtems_build_name(' ', '1', 'I', 'U')
0168   },
0169   { .event = TE(0, RTEMS_RECORD_THREAD_ID), .data = 0xa010002 },
0170   {
0171     .event = TE(0, RTEMS_RECORD_THREAD_NAME),
0172     .data = rtems_build_name('k', 'w', 't', 'n')
0173   },
0174   { .event = TE(0, RTEMS_RECORD_THREAD_ID), .data = 0xa010003 },
0175   {
0176     .event = TE(0, RTEMS_RECORD_THREAD_NAME),
0177     .data = rtems_build_name('D', 'R', 'C', 'R')
0178   }
0179 };
0180 #endif
0181
0182 static void init_context(test_context *ctx)
0183 {
0184   memset(ctx, 0, sizeof(*ctx));
0185   ctx->control.mask = ITEM_COUNT - 1;
0186 }
0187
0188 static void test_capacity(const Record_Control *control)
0189 {
0190   unsigned int capacity;
0191
0192   capacity = _Record_Capacity(control, 0, 0);
0193   rtems_test_assert(capacity == 3);
0194
0195   capacity = _Record_Capacity(control, 0, 1);
0196   rtems_test_assert(capacity == 2);
0197
0198   capacity = _Record_Capacity(control, 0, 2);
0199   rtems_test_assert(capacity == 1);
0200
0201   capacity = _Record_Capacity(control, 0, 3);
0202   rtems_test_assert(capacity == 0);
0203
0204   capacity = _Record_Capacity(control, 3, 3);
0205   rtems_test_assert(capacity == 3);
0206
0207   capacity = _Record_Capacity(control, 3, 0);
0208   rtems_test_assert(capacity == 2);
0209
0210   capacity = _Record_Capacity(control, 3, 1);
0211   rtems_test_assert(capacity == 1);
0212
0213   capacity = _Record_Capacity(control, 3, 2);
0214   rtems_test_assert(capacity == 0);
0215 }
0216
0217 static void test_index(const Record_Control *control)
0218 {
0219   unsigned int index;
0220
0221   index = _Record_Index(control, 0);
0222   rtems_test_assert(index == 0);
0223
0224   index = _Record_Index(control, 1);
0225   rtems_test_assert(index == 1);
0226
0227   index = _Record_Index(control, 2);
0228   rtems_test_assert(index == 2);
0229
0230   index = _Record_Index(control, 3);
0231   rtems_test_assert(index == 3);
0232
0233   index = _Record_Index(control, 4);
0234   rtems_test_assert(index == 0);
0235 }
0236
0237 static void test_add_2_items(test_context *ctx, Record_Control *control)
0238 {
0239   rtems_record_context rc;
0240
0241   init_context(ctx);
0242
0243   rtems_record_prepare(&rc);
0244   rtems_test_assert(rc.control == control);
0245   rtems_test_assert(rc.head == 0);
0246   rtems_test_assert(_Record_Head(control) == 0);
0247   rtems_test_assert(_Record_Tail(control) == 0);
0248
0249   rc.now = RTEMS_RECORD_TIME_EVENT(2, 0);
0250   rtems_record_add(&rc, UE(1), 3);
0251   rtems_test_assert(rc.head == 1);
0252   rtems_test_assert(memcmp(control->Items, expected_items_0, ITEM_SIZE) == 0);
0253   rtems_test_assert(_Record_Head(control) == 0);
0254   rtems_test_assert(_Record_Tail(control) == 0);
0255
0256   rc.now = RTEMS_RECORD_TIME_EVENT(6, 0);
0257   rtems_record_add(&rc, UE(5), 7);
0258   rtems_record_commit(&rc);
0259   rtems_test_assert(rc.head == 2);
0260   rtems_test_assert(memcmp(control->Items, expected_items_1, ITEM_SIZE) == 0);
0261   rtems_test_assert(_Record_Head(control) == 2);
0262   rtems_test_assert(_Record_Tail(control) == 0);
0263 }
0264
0265 static void test_add_3_items(test_context *ctx, Record_Control *control)
0266 {
0267   rtems_record_context rc;
0268   rtems_interrupt_level level;
0269
0270   init_context(ctx);
0271
0272   rtems_interrupt_local_disable(level);
0273   rtems_record_prepare_critical(&rc, _Per_CPU_Get());
0274   rtems_test_assert(rc.control == control);
0275   rtems_test_assert(rc.head == 0);
0276   rtems_test_assert(_Record_Head(control) == 0);
0277   rtems_test_assert(_Record_Tail(control) == 0);
0278
0279   rc.now = RTEMS_RECORD_TIME_EVENT(2, 0);
0280   rtems_record_add(&rc, UE(1), 3);
0281   rtems_test_assert(rc.head == 1);
0282   rtems_test_assert(memcmp(control->Items, expected_items_5, ITEM_SIZE) == 0);
0283   rtems_test_assert(_Record_Head(control) == 0);
0284   rtems_test_assert(_Record_Tail(control) == 0);
0285
0286   rc.now = RTEMS_RECORD_TIME_EVENT(6, 0);
0287   rtems_record_add(&rc, UE(5), 7);
0288   rtems_test_assert(rc.head == 2);
0289   rtems_test_assert(memcmp(control->Items, expected_items_6, ITEM_SIZE) == 0);
0290   rtems_test_assert(_Record_Head(control) == 0);
0291   rtems_test_assert(_Record_Tail(control) == 0);
0292
0293   rc.now = RTEMS_RECORD_TIME_EVENT(10, 0);
0294   rtems_record_add(&rc, UE(9), 11);
0295   rtems_record_commit_critical(&rc);
0296   rtems_interrupt_local_enable(level);
0297   rtems_test_assert(rc.head == 3);
0298   rtems_test_assert(memcmp(control->Items, expected_items_7, ITEM_SIZE) == 0);
0299   rtems_test_assert(_Record_Head(control) == 3);
0300   rtems_test_assert(_Record_Tail(control) == 0);
0301 }
0302
0303 static void set_time(rtems_record_item *item, uint32_t time)
0304 {
0305   uint32_t event;
0306
0307   event = item->event;
0308   event &= 0x3ff;
0309   event |= time << 10;
0310   item->event = event;
0311 }
0312
0313 static void test_produce(test_context *ctx, Record_Control *control)
0314 {
0315   init_context(ctx);
0316
0317   rtems_record_produce(UE(1), 3);
0318   set_time(&control->Items[0], 2);
0319   rtems_test_assert(memcmp(control->Items, expected_items_0, ITEM_SIZE) == 0);
0320   rtems_test_assert(_Record_Head(control) == 1);
0321   rtems_test_assert(_Record_Tail(control) == 0);
0322
0323   rtems_record_produce(UE(5), 7);
0324   set_time(&control->Items[1], 6);
0325   rtems_test_assert(memcmp(control->Items, expected_items_1, ITEM_SIZE) == 0);
0326   rtems_test_assert(_Record_Head(control) == 2);
0327   rtems_test_assert(_Record_Tail(control) == 0);
0328
0329   rtems_record_produce(UE(9), 11);
0330   set_time(&control->Items[2], 10);
0331   rtems_test_assert(memcmp(control->Items, expected_items_2, ITEM_SIZE) == 0);
0332   rtems_test_assert(_Record_Head(control) == 3);
0333   rtems_test_assert(_Record_Tail(control) == 0);
0334
0335   rtems_record_produce(UE(13), 15);
0336   set_time(&control->Items[3], 14);
0337   rtems_test_assert(memcmp(control->Items, expected_items_3, ITEM_SIZE) == 0);
0338   rtems_test_assert(_Record_Head(control) == 4);
0339   rtems_test_assert(_Record_Tail(control) == 0);
0340
0341   rtems_record_produce(UE(17), 19);
0342   set_time(&control->Items[0], 18);
0343   rtems_test_assert(memcmp(control->Items, expected_items_4, ITEM_SIZE) == 0);
0344   rtems_test_assert(_Record_Head(control) == 5);
0345   rtems_test_assert(_Record_Tail(control) == 0);
0346 }
0347
0348 static void test_produce_2(test_context *ctx, Record_Control *control)
0349 {
0350   init_context(ctx);
0351
0352   rtems_record_produce_2(UE(1), 3, UE(5), 7);
0353   set_time(&control->Items[0], 2);
0354   set_time(&control->Items[1], 6);
0355   rtems_test_assert(memcmp(control->Items, expected_items_1, ITEM_SIZE) == 0);
0356   rtems_test_assert(_Record_Head(control) == 2);
0357   rtems_test_assert(_Record_Tail(control) == 0);
0358
0359   rtems_record_produce(UE(9), 11);
0360   set_time(&control->Items[2], 10);
0361   rtems_test_assert(memcmp(control->Items, expected_items_2, ITEM_SIZE) == 0);
0362   rtems_test_assert(_Record_Head(control) == 3);
0363   rtems_test_assert(_Record_Tail(control) == 0);
0364
0365   rtems_record_produce_2(UE(13), 15, UE(17), 19);
0366   set_time(&control->Items[3], 14);
0367   set_time(&control->Items[0], 18);
0368   rtems_test_assert(memcmp(control->Items, expected_items_4, ITEM_SIZE) == 0);
0369   rtems_test_assert(_Record_Head(control) == 5);
0370   rtems_test_assert(_Record_Tail(control) == 0);
0371 }
0372
0373 static void test_produce_n(test_context *ctx, Record_Control *control)
0374 {
0375   rtems_record_item items[5];
0376
0377   init_context(ctx);
0378
0379   items[0].event = UE(1);
0380   items[0].data = 3;
0381   items[1].event = UE(5);
0382   items[1].data = 7;
0383   items[2].event = UE(9);
0384   items[2].data = 11;
0385   items[3].event = UE(13);
0386   items[3].data = 15;
0387   items[4].event = UE(17);
0388   items[4].data = 19;
0389   rtems_record_produce_n(items, RTEMS_ARRAY_SIZE(items));
0390   set_time(&control->Items[1], 6);
0391   set_time(&control->Items[2], 10);
0392   set_time(&control->Items[3], 14);
0393   set_time(&control->Items[0], 18);
0394   rtems_test_assert(memcmp(control->Items, expected_items_4, ITEM_SIZE) == 0);
0395   rtems_test_assert(_Record_Head(control) == 5);
0396   rtems_test_assert(_Record_Tail(control) == 0);
0397 }
0398
0399 #ifdef RTEMS_NETWORKING
0400 #define PORT 1234
0401
0402 typedef enum {
0403   HEADER_ARCH,
0404   HEADER_MULTILIB,
0405   HEADER_BSP,
0406   HEADER_VERSION_CONTROL_KEY,
0407   HEADER_TOOLS,
0408   HEADER_LAST
0409 } header_state;
0410
0411 static uint32_t get_format(void)
0412 {
0413   uint32_t format;
0414
0415 #if BYTE_ORDER == LITTLE_ENDIAN
0416 #if __INTPTR_WIDTH__ == 32
0417   format = RTEMS_RECORD_FORMAT_LE_32;
0418 #elif __INTPTR_WIDTH__ == 64
0419   format = RTEMS_RECORD_FORMAT_LE_64;
0420 #else
0421 #error "unexpected __INTPTR_WIDTH__"
0422 #endif
0423 #elif BYTE_ORDER == BIG_ENDIAN
0424 #if __INTPTR_WIDTH__ == 32
0425   format = RTEMS_RECORD_FORMAT_BE_32;
0426 #elif __INTPTR_WIDTH__ == 64
0427   format = RTEMS_RECORD_FORMAT_BE_64;
0428 #else
0429 #error "unexpected __INTPTR_WIDTH__"
0430 #endif
0431 #else
0432 #error "unexpected BYTE_ORDER"
0433 #endif
0434
0435   return format;
0436 }
0437
0438 static rtems_record_event hs_to_ev(header_state hs)
0439 {
0440   switch (hs) {
0441     case HEADER_ARCH:
0442       return RTEMS_RECORD_ARCH;
0443     case HEADER_MULTILIB:
0444       return RTEMS_RECORD_MULTILIB;
0445     case HEADER_BSP:
0446       return RTEMS_RECORD_BSP;
0447     case HEADER_VERSION_CONTROL_KEY:
0448       return RTEMS_RECORD_VERSION_CONTROL_KEY;
0449     case HEADER_TOOLS:
0450       return RTEMS_RECORD_TOOLS;
0451     default:
0452       rtems_test_assert(0);
0453       return RTEMS_RECORD_EMPTY;
0454   }
0455 }
0456
0457 static int connect_client(void)
0458 {
0459   struct sockaddr_in addr;
0460   int fd;
0461   int rv;
0462   ssize_t n;
0463   uint32_t v;
0464   rtems_record_item item;
0465   rtems_record_item items[8];
0466   header_state hs;
0467
0468   fd = socket(PF_INET, SOCK_STREAM, 0);
0469   rtems_test_assert(fd >= 0);
0470
0471   memset(&addr, 0, sizeof(addr));
0472   addr.sin_family = AF_INET;
0473   addr.sin_port = htons(PORT);
0474   addr.sin_addr.s_addr = htonl(INADDR_ANY);
0475   rv = connect(fd, (struct sockaddr *) &addr, sizeof(addr));
0476   rtems_test_assert(rv == 0);
0477
0478   n = read(fd, &v, sizeof(v));
0479   rtems_test_assert(n == 4);
0480   rtems_test_assert(v == get_format());
0481
0482   n = read(fd, &v, sizeof(v));
0483   rtems_test_assert(n == 4);
0484   rtems_test_assert(v == RTEMS_RECORD_MAGIC);
0485
0486   n = read(fd, &item, sizeof(item));
0487   rtems_test_assert(n == (ssize_t) sizeof(item));
0488   rtems_test_assert(item.event == TE(0, RTEMS_RECORD_VERSION));
0489   rtems_test_assert(item.data == RTEMS_RECORD_THE_VERSION);
0490
0491   n = read(fd, &item, sizeof(item));
0492   rtems_test_assert(n == (ssize_t) sizeof(item));
0493   rtems_test_assert(item.event == TE(0, RTEMS_RECORD_PROCESSOR_MAXIMUM));
0494   rtems_test_assert(item.data == 0);
0495
0496   n = read(fd, &item, sizeof(item));
0497   rtems_test_assert(n == (ssize_t) sizeof(item));
0498   rtems_test_assert(item.event == TE(0, RTEMS_RECORD_PER_CPU_COUNT));
0499   rtems_test_assert(item.data == ITEM_COUNT);
0500
0501   n = read(fd, &item, sizeof(item));
0502   rtems_test_assert(n == (ssize_t) sizeof(item));
0503   rtems_test_assert(item.event == TE(0, RTEMS_RECORD_FREQUENCY));
0504   rtems_test_assert(item.data == rtems_counter_frequency());
0505
0506   hs = HEADER_ARCH;
0507   while (hs != HEADER_LAST) {
0508     n = read(fd, items, sizeof(items[0]));
0509     rtems_test_assert(n == (ssize_t) sizeof(items[0]));
0510
0511     if (items[0].event != hs_to_ev(hs)) {
0512       ++hs;
0513     }
0514
0515     rtems_test_assert(hs == HEADER_LAST || items[0].event == hs_to_ev(hs));
0516   }
0517
0518   n = read(fd, &items[1], sizeof(expected_items_13) - sizeof(items[0]));
0519   rtems_test_assert(
0520     n == (ssize_t) (sizeof(expected_items_13) - sizeof(items[0]))
0521   );
0522   rtems_test_assert(
0523     memcmp(items, expected_items_13, sizeof(expected_items_13)) == 0
0524   );
0525
0526   return fd;
0527 }
0528
0529 static void produce_and_read(int fd, Record_Control *control)
0530 {
0531   rtems_record_item items[6];
0532   ssize_t n;
0533
0534   rtems_record_produce(UE(1), 3);
0535   set_time(&control->Items[0], 2);
0536   rtems_record_produce(UE(4), 6);
0537   set_time(&control->Items[1], 5);
0538   rtems_record_produce(UE(7), 9);
0539   set_time(&control->Items[2], 8);
0540
0541   n = read(fd, items, sizeof(expected_items_8));
0542   rtems_test_assert(n == (ssize_t) sizeof(expected_items_8));
0543   rtems_test_assert(
0544     memcmp(items, expected_items_8, sizeof(expected_items_8)) == 0
0545   );
0546
0547   rtems_record_produce(UE(10), 12);
0548   set_time(&control->Items[3], 11);
0549   rtems_record_produce(UE(13), 15);
0550   set_time(&control->Items[0], 14);
0551
0552   n = read(fd, items, sizeof(expected_items_9));
0553   rtems_test_assert(n == (ssize_t) sizeof(expected_items_9));
0554   rtems_test_assert(
0555     memcmp(items, expected_items_9, sizeof(expected_items_9)) == 0
0556   );
0557
0558   rtems_record_produce(UE(16), 18);
0559   set_time(&control->Items[1], 17);
0560   rtems_record_produce(UE(19), 21);
0561   set_time(&control->Items[2], 20);
0562   rtems_record_produce(UE(22), 24);
0563   set_time(&control->Items[3], 23);
0564
0565   n = read(fd, items, sizeof(expected_items_10));
0566   rtems_test_assert(n == (ssize_t) sizeof(expected_items_10));
0567   rtems_test_assert(
0568     memcmp(items, expected_items_10, sizeof(expected_items_10)) == 0
0569   );
0570
0571   rtems_record_produce(UE(25), 27);
0572   set_time(&control->Items[0], 26);
0573
0574   n = read(fd, items, sizeof(expected_items_11));
0575   rtems_test_assert(n == (ssize_t) sizeof(expected_items_11));
0576   rtems_test_assert(
0577     memcmp(items, expected_items_11, sizeof(expected_items_11)) == 0
0578   );
0579
0580   rtems_record_produce(UE(28), 30);
0581   set_time(&control->Items[1], 29);
0582   rtems_record_produce(UE(31), 33);
0583   set_time(&control->Items[2], 32);
0584   rtems_record_produce(UE(34), 36);
0585   set_time(&control->Items[3], 35);
0586   rtems_record_produce(UE(37), 39);
0587   set_time(&control->Items[0], 38);
0588   rtems_record_produce(UE(40), 42);
0589   set_time(&control->Items[1], 41);
0590   rtems_record_produce(UE(43), 45);
0591   set_time(&control->Items[2], 44);
0592
0593   n = read(fd, items, sizeof(expected_items_12));
0594   rtems_test_assert(n == (ssize_t) sizeof(expected_items_12));
0595   rtems_test_assert(
0596     memcmp(items, expected_items_12, sizeof(expected_items_12)) == 0
0597   );
0598 }
0599
0600 static void test_server(test_context *ctx, Record_Control *control)
0601 {
0602   rtems_status_code sc;
0603   int rv;
0604   int fd;
0605
0606   init_context(ctx);
0607
0608   rv = rtems_bsdnet_initialize_network();
0609   rtems_test_assert(rv == 0);
0610
0611   sc = rtems_record_start_server(1, PORT, 1);
0612   rtems_test_assert(sc == RTEMS_SUCCESSFUL);
0613
0614   fd = connect_client();
0615   produce_and_read(fd, control);
0616
0617   rv = close(fd);
0618   rtems_test_assert(rv == 0);
0619 }
0620 #endif
0621
0622 static void Init(rtems_task_argument arg)
0623 {
0624   test_context *ctx;
0625   Per_CPU_Control *cpu_self;
0626
0627   TEST_BEGIN();
0628
0629   ctx = &test_instance;
0630
0631   cpu_self = _Per_CPU_Get_snapshot();
0632   cpu_self->record = &ctx->control;
0633
0634   init_context(ctx);
0635   test_capacity(&ctx->control);
0636   test_index(&ctx->control);
0637   test_add_2_items(ctx, &ctx->control);
0638   test_add_3_items(ctx, &ctx->control);
0639   test_produce(ctx, &ctx->control);
0640   test_produce_2(ctx, &ctx->control);
0641   test_produce_n(ctx, &ctx->control);
0642 #ifdef RTEMS_NETWORKING
0643   test_server(ctx, &ctx->control);
0644 #endif
0645
0646   TEST_END();
0647   rtems_test_exit(0);
0648 }
0649
0650 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
0651
0652 #define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER
0653
0654 #ifdef RTEMS_NETWORKING
0655 #define CONFIGURE_MAXIMUM_FILE_DESCRIPTORS 7
0656
0657 #define CONFIGURE_MAXIMUM_TASKS 3
0658
0659 #define CONFIGURE_MAXIMUM_TIMERS 1
0660
0661 #define CONFIGURE_INIT_TASK_ATTRIBUTES RTEMS_FLOATING_POINT
0662 #else
0663 #define CONFIGURE_MAXIMUM_TASKS 1
0664 #endif
0665
0666 #define CONFIGURE_INIT_TASK_PRIORITY 2
0667
0668 #define CONFIGURE_INIT_TASK_INITIAL_MODES RTEMS_DEFAULT_MODES
0669
0670 #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
0671
0672 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
0673
0674 #define CONFIGURE_INIT
0675
0676 #include <rtems/confdefs.h>