Warning, /spec/build/bsps/sparc/leon3/optdsubase.yml is written in an unsupported language. File is not indexed.
0001 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
0002 copyrights:
0003 - Copyright (C) 2023 embedded brains GmbH & Co. KG
0004 actions:
0005 - get-integer: null
0006 - format-and-define: null
0007 build-type: option
0008 default:
0009 - enabled-by: sparc/gr712rc
0010 value: 0x90000000
0011 enabled-by: true
0012 format: '{:#010x}'
0013 links: []
0014 name: LEON3_DSU_BASE
0015 description: |
0016 This option defines the base address of the DSU register block used by
0017 the clock driver and CPU counter implementation.
0018
0019 In general, using the Debug Support Unit (DSU) is not recommended for the
0020 clock driver and CPU counter implementation. Before you use it, check that
0021 it is available in flight models and that the time tag register is
0022 implemented in radiation hardened flip-flops. For the GR712RC, this is the
0023 case.
0024 type: build
