Warning, /spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml is written in an unsupported language. File is not indexed.
0001 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
0002 actions:
0003 - get-boolean: null
0004 - define-condition: null
0005 build-type: option
0006 copyrights:
0007 - Copyright (C) 2024 embedded brains GmbH & Co. KG
0008 default:
0009 - enabled-by:
0010 - bsps/arm/altera-cyclone-v
0011 - bsps/arm/xilinx-zynq
0012 value: true
0013 - enabled-by: true
0014 value: false
0015 description: |
0016 This option enables the use FIQ interrupts for GIC group 0 interrupts. The
0017 ARM Generic Interrupt Controller (GIC) variants GICv1 with Security
0018 Extensions, GICv2 without Security Extensions, GICv2 with Security Extensions
0019 and in Secure processor mode, GICv3 and GICv4 in Secure processor mode, GICv3
0020 and GICv4 with GICD_CTLR.DS == 1 have the ability to assign group 0 or 1 to
0021 individual interrupts. Group 0 interrupts can be configured to raise an FIQ
0022 exception. This enables the use of NMIs with respect to RTEMS. Use
0023 arm_gic_irq_set_group() to change the group of an interrupt (default group is
0024 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined). To use FIQ interrupts,
0025 you have to install an FIQ exception handler and enable FIQs in the Current
0026 Program Status Register (CPSR).
0027 enabled-by: true
0028 format: '{}'
0029 links: []
0030 name: BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
0031 type: build
