Warning, /spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml is written in an unsupported language. File is not indexed.
0001 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
0002 build-type: config-file
0003 content: |
0004 MEMORY {
0005 NULL : ORIGIN = 0x00000000, LENGTH = ${STM32H7_MEMORY_NULL_SIZE:#010x}
0006 ITCM : ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH = ${STM32H7_MEMORY_ITCM_SIZE:#010x}
0007 FLASH : ORIGIN = ${STM32H7_MEMORY_FLASH_ORIGIN:#010x}, LENGTH = ${STM32H7_MEMORY_FLASH_SIZE:#010x}
0008 DTCM : ORIGIN = 0x20000000, LENGTH = ${STM32H7_MEMORY_DTCM_SIZE:#010x}
0009 SRAM_AXI : ORIGIN = 0x24000000, LENGTH = ${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x}
0010 SRAM_1 : ORIGIN = 0x30000000, LENGTH = ${STM32H7_MEMORY_SRAM_1_SIZE:#010x}
0011 SRAM_2 : ORIGIN = 0x30020000, LENGTH = ${STM32H7_MEMORY_SRAM_2_SIZE:#010x}
0012 SRAM_3 : ORIGIN = 0x30040000, LENGTH = ${STM32H7_MEMORY_SRAM_3_SIZE:#010x}
0013 SRAM_4 : ORIGIN = 0x38000000, LENGTH = ${STM32H7_MEMORY_SRAM_4_SIZE:#010x}
0014 SRAM_BACKUP : ORIGIN = 0x38800000, LENGTH = ${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x}
0015 PERIPHERAL : ORIGIN = 0x40000000, LENGTH = ${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x}
0016 NOR : ORIGIN = 0x60000000, LENGTH = ${STM32H7_MEMORY_NOR_SIZE:#010x}
0017 SDRAM_1 : ORIGIN = 0x70000000, LENGTH = ${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
0018 NAND : ORIGIN = 0x80000000, LENGTH = ${STM32H7_MEMORY_NAND_SIZE:#010x}
0019 QUADSPI : ORIGIN = 0x90000000, LENGTH = ${STM32H7_MEMORY_QUADSPI_SIZE:#010x}
0020 SDRAM_2 : ORIGIN = 0xd0000000, LENGTH = ${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}
0021 }
0022
0023 stm32h7_memory_null_begin = ORIGIN (NULL);
0024 stm32h7_memory_null_end = ORIGIN (NULL) + LENGTH (NULL);
0025 stm32h7_memory_null_size = LENGTH (NULL);
0026
0027 stm32h7_memory_itcm_begin = ORIGIN (ITCM);
0028 stm32h7_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM);
0029 stm32h7_memory_itcm_size = LENGTH (ITCM);
0030
0031 stm32h7_memory_flash_begin = ORIGIN (FLASH);
0032 stm32h7_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH);
0033 stm32h7_memory_flash_size = LENGTH (FLASH);
0034
0035 stm32h7_memory_dtcm_begin = ORIGIN (DTCM);
0036 stm32h7_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM);
0037 stm32h7_memory_dtcm_size = LENGTH (DTCM);
0038
0039 stm32h7_memory_sram_axi_begin = ORIGIN (SRAM_AXI);
0040 stm32h7_memory_sram_axi_end = ORIGIN (SRAM_AXI) + LENGTH (SRAM_AXI);
0041 stm32h7_memory_sram_axi_size = LENGTH (SRAM_AXI);
0042
0043 stm32h7_memory_sram_1_begin = ORIGIN (SRAM_1);
0044 stm32h7_memory_sram_1_end = ORIGIN (SRAM_1) + LENGTH (SRAM_1);
0045 stm32h7_memory_sram_1_size = LENGTH (SRAM_1);
0046
0047 stm32h7_memory_sram_2_begin = ORIGIN (SRAM_2);
0048 stm32h7_memory_sram_2_end = ORIGIN (SRAM_2) + LENGTH (SRAM_2);
0049 stm32h7_memory_sram_2_size = LENGTH (SRAM_2);
0050
0051 stm32h7_memory_sram_3_begin = ORIGIN (SRAM_3);
0052 stm32h7_memory_sram_3_end = ORIGIN (SRAM_3) + LENGTH (SRAM_3);
0053 stm32h7_memory_sram_3_size = LENGTH (SRAM_3);
0054
0055 stm32h7_memory_sram_4_begin = ORIGIN (SRAM_4);
0056 stm32h7_memory_sram_4_end = ORIGIN (SRAM_4) + LENGTH (SRAM_4);
0057 stm32h7_memory_sram_4_size = LENGTH (SRAM_4);
0058
0059 stm32h7_memory_sram_backup_begin = ORIGIN (SRAM_BACKUP);
0060 stm32h7_memory_sram_backup_end = ORIGIN (SRAM_BACKUP) + LENGTH (SRAM_BACKUP);
0061 stm32h7_memory_sram_backup_size = LENGTH (SRAM_BACKUP);
0062
0063 stm32h7_memory_peripheral_begin = ORIGIN (PERIPHERAL);
0064 stm32h7_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL);
0065 stm32h7_memory_peripheral_size = LENGTH (PERIPHERAL);
0066
0067 stm32h7_memory_nor_begin = ORIGIN (NOR);
0068 stm32h7_memory_nor_end = ORIGIN (NOR) + LENGTH (NOR);
0069 stm32h7_memory_nor_size = LENGTH (NOR);
0070
0071 stm32h7_memory_sdram_1_begin = ORIGIN (SDRAM_1);
0072 stm32h7_memory_sdram_1_end = ORIGIN (SDRAM_1) + LENGTH (SDRAM_1);
0073 stm32h7_memory_sdram_1_size = LENGTH (SDRAM_1);
0074
0075 stm32h7_memory_nand_begin = ORIGIN (NAND);
0076 stm32h7_memory_nand_end = ORIGIN (NAND) + LENGTH (NAND);
0077 stm32h7_memory_nand_size = LENGTH (NAND);
0078
0079 stm32h7_memory_quadspi_begin = ORIGIN (QUADSPI);
0080 stm32h7_memory_quadspi_end = ORIGIN (QUADSPI) + LENGTH (QUADSPI);
0081 stm32h7_memory_quadspi_size = LENGTH (QUADSPI);
0082
0083 stm32h7_memory_sdram_2_begin = ORIGIN (SDRAM_2);
0084 stm32h7_memory_sdram_2_end = ORIGIN (SDRAM_2) + LENGTH (SDRAM_2);
0085 stm32h7_memory_sdram_2_size = LENGTH (SDRAM_2);
0086 copyrights:
0087 - Copyright (C) 2020 embedded brains GmbH & Co. KG
0088 enabled-by: true
0089 install-path: ${BSP_LIBDIR}
0090 links: []
0091 target: linkcmds.memory
0092 type: build
