Warning, /spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml is written in an unsupported language. File is not indexed.
0001 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
0002 build-type: config-file
0003 content: |
0004 /* SPDX-License-Identifier: BSD-2-Clause */
0005
0006 /*
0007 * Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
0008 * Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
0009 *
0010 * Redistribution and use in source and binary forms, with or without
0011 * modification, are permitted provided that the following conditions
0012 * are met:
0013 * 1. Redistributions of source code must retain the above copyright
0014 * notice, this list of conditions and the following disclaimer.
0015 * 2. Redistributions in binary form must reproduce the above copyright
0016 * notice, this list of conditions and the following disclaimer in the
0017 * documentation and/or other materials provided with the distribution.
0018 *
0019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0023 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0024 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0025 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0026 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0027 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0028 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0029 * POSSIBILITY OF SUCH DAMAGE.
0030 */
0031
0032 /*
0033 * The RAM supports 32G of DDR4 or LPDDR memory using DDRMC0.
0034 *
0035 * The DDR Conroller (DDRC) has two regions R0 and R1. R0 is
0036 * in the A32 address space and R1 is in the A64 address space.
0037 */
0038 DDRMC0_REGION_0_BASE = 0x00000000000;
0039 DDRMC0_REGION_0_LENGTH = 0x00080000000;
0040 DDRMC0_REGION_1_BASE = 0x00800000000;
0041 DDRMC0_REGION_1_LENGTH = 0x01000000000;
0042
0043 BSP_RAM_BASE = ${BSP_XILINX_VERSAL_RAM_BASE};
0044
0045 BSP_R0_RAM_BASE = DDRMC0_REGION_0_BASE;
0046 BSP_R0_RAM_LENGTH =
0047 ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
0048 DDRMC0_REGION_0_LENGTH - BSP_RAM_BASE : ${BSP_XILINX_VERSAL_RAM_LENGTH};
0049 BSP_R0_RAM_END = BSP_RAM_BASE + BSP_R0_RAM_LENGTH;
0050
0051 BSP_R1_RAM_BASE = DDRMC0_REGION_1_BASE;
0052 BSP_R1_RAM_LENGTH =
0053 ${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
0054 ${BSP_XILINX_VERSAL_RAM_LENGTH} - DDRMC0_REGION_0_LENGTH : 0;
0055
0056 AARCH64_MMU_TT_PAGES_SIZE = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES};
0057
0058 MEMORY {
0059 RAM : ORIGIN = BSP_RAM_BASE + ${BSP_XILINX_VERSAL_LOAD_OFFSET},
0060 LENGTH = BSP_R0_RAM_LENGTH - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - AARCH64_MMU_TT_PAGES_SIZE
0061 RAM1 : ORIGIN = BSP_R1_RAM_BASE,
0062 LENGTH = BSP_R1_RAM_LENGTH
0063 NOCACHE : ORIGIN = BSP_RAM_BASE + BSP_R0_RAM_LENGTH - AARCH64_MMU_TT_PAGES_SIZE - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
0064 LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
0065 RAM_MMU : ORIGIN = BSP_R0_RAM_END - AARCH64_MMU_TT_PAGES_SIZE,
0066 LENGTH = AARCH64_MMU_TT_PAGES_SIZE
0067 }
0068
0069 REGION_ALIAS ("REGION_START", RAM);
0070 REGION_ALIAS ("REGION_VECTOR", RAM);
0071 REGION_ALIAS ("REGION_TEXT", RAM);
0072 REGION_ALIAS ("REGION_TEXT_LOAD", RAM);
0073 REGION_ALIAS ("REGION_RODATA", RAM);
0074 REGION_ALIAS ("REGION_RODATA_LOAD", RAM);
0075 REGION_ALIAS ("REGION_DATA", RAM);
0076 REGION_ALIAS ("REGION_DATA_LOAD", RAM);
0077 REGION_ALIAS ("REGION_FAST_TEXT", RAM);
0078 REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
0079 REGION_ALIAS ("REGION_FAST_DATA", RAM);
0080 REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
0081 REGION_ALIAS ("REGION_BSS", RAM);
0082 REGION_ALIAS ("REGION_WORK", RAM);
0083 REGION_ALIAS ("REGION_STACK", RAM);
0084 REGION_ALIAS ("REGION_NOCACHE", NOCACHE);
0085 REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
0086
0087 bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;
0088
0089 bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
0090
0091 bsp_vector_table_in_start_section = 1;
0092
0093 bsp_r0_ram_base = DDRMC0_REGION_0_BASE;
0094 bsp_r0_ram_end = ORIGIN (RAM) + LENGTH (RAM);
0095 bsp_r1_ram_base = ORIGIN (RAM1);
0096 bsp_r1_ram_end = ORIGIN (RAM1) + LENGTH (RAM1);
0097
0098 bsp_translation_table_base = ORIGIN (RAM_MMU);
0099 bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
0100
0101 OUTPUT_FORMAT ("elf64-littleaarch64")
0102 OUTPUT_ARCH (aarch64)
0103
0104 INCLUDE linkcmds.base
0105 copyrights:
0106 - Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
0107 - Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
0108 enabled-by: true
0109 install-path: ${BSP_LIBDIR}
0110 links: []
0111 target: linkcmds
0112 type: build
