score/src/smpbarrierwait.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreSMPBarrier
0007  *
0008  * @brief This source file contains the implementation of
0009  *   _SMP_barrier_Wait().
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/smpbarrier.h>
0042
0043 bool _SMP_barrier_Wait(
0044   SMP_barrier_Control *control,
0045   SMP_barrier_State *state,
0046   unsigned int count
0047 )
0048 {
0049   unsigned int sense = ~state->sense;
0050   unsigned int previous_value;
0051   bool performed_release;
0052
0053   state->sense = sense;
0054
0055   previous_value = _Atomic_Fetch_add_uint(
0056     &control->value,
0057     1U,
0058     ATOMIC_ORDER_RELAXED
0059   );
0060
0061   if ( previous_value + 1U == count ) {
0062     _Atomic_Store_uint( &control->value, 0U, ATOMIC_ORDER_RELAXED );
0063     _Atomic_Store_uint( &control->sense, sense, ATOMIC_ORDER_RELEASE );
0064     performed_release = true;
0065   } else {
0066     while (
0067       _Atomic_Load_uint( &control->sense, ATOMIC_ORDER_ACQUIRE ) != sense
0068     ) {
0069       /* Wait */
0070     }
0071
0072     performed_release = false;
0073   }
0074
0075   return performed_release;
0076 }