score/src/percpuasm.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScorePerCPU
0007  *
0008  * @brief This source file contains the static assertions for defines used in
0009  *   assembler files.
0010  */
0011
0012 /*
0013  * Copyright (C) 2012, 2016 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/cpu.h>
0042
0043 #define _RTEMS_PERCPU_DEFINE_OFFSETS
0044 #include <rtems/score/percpu.h>
0045
0046 #define PER_CPU_IS_POWER_OF_TWO( value ) \
0047   ( ( value ) > 1 && ( ( ( value ) - 1 ) & ( value ) ) == 0 )
0048
0049 /*
0050  * The minimum alignment of two is due to the Heap Handler which uses the
0051  * HEAP_PREV_BLOCK_USED flag to indicate that the previous block is used.
0052  */
0053
0054 RTEMS_STATIC_ASSERT(
0055   CPU_ALIGNMENT >= 2 && PER_CPU_IS_POWER_OF_TWO( CPU_ALIGNMENT ),
0056   CPU_ALIGNMENT
0057 );
0058
0059 RTEMS_STATIC_ASSERT(
0060   CPU_HEAP_ALIGNMENT >= 2 && PER_CPU_IS_POWER_OF_TWO( CPU_HEAP_ALIGNMENT ),
0061   CPU_HEAP_ALIGNMENT_0
0062 );
0063
0064 RTEMS_STATIC_ASSERT(
0065   CPU_HEAP_ALIGNMENT >= CPU_ALIGNMENT,
0066   CPU_HEAP_ALIGNMENT_1
0067 );
0068
0069 RTEMS_STATIC_ASSERT(
0070   CPU_STACK_ALIGNMENT >= CPU_HEAP_ALIGNMENT &&
0071     PER_CPU_IS_POWER_OF_TWO( CPU_STACK_ALIGNMENT ),
0072   CPU_STACK_ALIGNMENT
0073 );
0074
0075 RTEMS_STATIC_ASSERT(
0076   PER_CPU_IS_POWER_OF_TWO( CPU_STACK_MINIMUM_SIZE ),
0077   CPU_STACK_MINIMUM_SIZE
0078 );
0079
0080 RTEMS_STATIC_ASSERT(
0081   sizeof(void *) == CPU_SIZEOF_POINTER,
0082   CPU_SIZEOF_POINTER
0083 );
0084
0085 #if defined( __SIZEOF_POINTER__ )
0086   RTEMS_STATIC_ASSERT(
0087     CPU_SIZEOF_POINTER == __SIZEOF_POINTER__,
0088     __SIZEOF_POINTER__
0089   );
0090 #endif
0091
0092 #if CPU_PER_CPU_CONTROL_SIZE > 0
0093   RTEMS_STATIC_ASSERT(
0094     sizeof( CPU_Per_CPU_control ) == CPU_PER_CPU_CONTROL_SIZE,
0095     CPU_PER_CPU_CONTROL_SIZE
0096   );
0097 #endif
0098
0099 #if defined( RTEMS_SMP )
0100   RTEMS_STATIC_ASSERT(
0101     sizeof( Per_CPU_Control_envelope ) == PER_CPU_CONTROL_SIZE,
0102     PER_CPU_CONTROL_SIZE
0103   );
0104 #endif
0105
0106 RTEMS_STATIC_ASSERT(
0107   offsetof(Per_CPU_Control, isr_nest_level) == PER_CPU_ISR_NEST_LEVEL,
0108   PER_CPU_ISR_NEST_LEVEL
0109 );
0110
0111 RTEMS_STATIC_ASSERT(
0112   offsetof(Per_CPU_Control, isr_dispatch_disable)
0113     == PER_CPU_ISR_DISPATCH_DISABLE,
0114   PER_CPU_ISR_DISPATCH_DISABLE
0115 );
0116
0117 RTEMS_STATIC_ASSERT(
0118   offsetof(Per_CPU_Control, thread_dispatch_disable_level)
0119     == PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL,
0120   PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL
0121 );
0122
0123 RTEMS_STATIC_ASSERT(
0124   offsetof(Per_CPU_Control, executing) == PER_CPU_OFFSET_EXECUTING,
0125   PER_CPU_OFFSET_EXECUTING
0126 );
0127
0128 RTEMS_STATIC_ASSERT(
0129   offsetof(Per_CPU_Control, heir) == PER_CPU_OFFSET_HEIR,
0130   PER_CPU_OFFSET_HEIR
0131 );
0132
0133 RTEMS_STATIC_ASSERT(
0134   offsetof(Per_CPU_Control, dispatch_necessary) == PER_CPU_DISPATCH_NEEDED,
0135   PER_CPU_DISPATCH_NEEDED
0136 );
0137
0138 #if defined(RTEMS_SMP)
0139 RTEMS_STATIC_ASSERT(
0140   offsetof(Per_CPU_Control, Interrupt_frame) == PER_CPU_INTERRUPT_FRAME_AREA,
0141   PER_CPU_INTERRUPT_FRAME_AREA
0142 );
0143
0144 RTEMS_STATIC_ASSERT(
0145   sizeof( CPU_Interrupt_frame ) == CPU_INTERRUPT_FRAME_SIZE,
0146   CPU_INTERRUPT_FRAME_SIZE
0147 );
0148 #endif
0149
0150 RTEMS_STATIC_ASSERT(
0151   offsetof(Per_CPU_Control, interrupt_stack_low)
0152     == PER_CPU_INTERRUPT_STACK_LOW,
0153   PER_CPU_INTERRUPT_STACK_LOW
0154 );
0155
0156 RTEMS_STATIC_ASSERT(
0157   offsetof(Per_CPU_Control, interrupt_stack_high)
0158     == PER_CPU_INTERRUPT_STACK_HIGH,
0159   PER_CPU_INTERRUPT_STACK_HIGH
0160 );