score/src/exceptionmapping.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreExceptionMapping
0007  *
0008  * @brief AArch64 machine exception to POSIX signal mapping.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <pthread.h>
0038 #include <signal.h>
0039 #include <rtems/score/exception.h>
0040 #include <rtems/score/thread.h>
0041 #include <rtems/score/threadimpl.h>
0042
0043 static _Thread_local int           raise_signal;
0044 static _Thread_local Thread_Action _Exception_Raise_signal_action;
0045
0046 static void _Exception_Raise_handler(
0047   Thread_Control   *executing,
0048   Thread_Action    *action,
0049   ISR_lock_Context *lock_context
0050 )
0051 {
0052   _Thread_State_release( executing, lock_context );
0053   raise( raise_signal );
0054   _Thread_State_acquire( executing, lock_context );
0055 }
0056
0057 /*
0058  * Exception handler. Map the exception class to SIGFPE, SIGSEGV
0059  * or SIGILL for Ada or other runtimes.
0060  */
0061 void _Exception_Raise_signal(
0062   Internal_errors_Source source,
0063   bool                   always_set_to_false,
0064   Internal_errors_t      code
0065 )
0066 {
0067   CPU_Exception_frame *ef;
0068   Per_CPU_Control     *cpu_self = _Per_CPU_Get();
0069   bool                 system_up;
0070
0071   if ( source != RTEMS_FATAL_SOURCE_EXCEPTION ) {
0072     return;
0073   }
0074
0075   /* If the CPU isn't UP yet, there isn't anything to send a signal to */
0076 #ifdef RTEMS_SMP
0077   system_up = ( _Per_CPU_Get_state( cpu_self ) == PER_CPU_STATE_UP );
0078 #else
0079   system_up = ( _System_state_Get() == SYSTEM_STATE_UP );
0080 #endif
0081
0082   if ( !system_up ) {
0083     return;
0084   }
0085
0086   ef = (rtems_exception_frame *) code;
0087   raise_signal = _CPU_Exception_frame_get_signal( ef );
0088
0089   if ( raise_signal < 0 ) {
0090     return;
0091   }
0092
0093   _Thread_Add_post_switch_action(
0094     _Per_CPU_Get_executing( cpu_self ),
0095     &_Exception_Raise_signal_action,
0096     _Exception_Raise_handler
0097   );
0098
0099   /* Disable thread dispatch so that dispatch can occur */
0100   _CPU_Exception_disable_thread_dispatch();
0101
0102   /* Perform dispatch and resume execution */
0103   _CPU_Exception_dispatch_and_resume( ef );
0104 }