cpu/v850/cpu.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief v850 CPU Initialize
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifdef HAVE_CONFIG_H
0036 #include "config.h"
0037 #endif
0038
0039 #include <rtems/score/cpuimpl.h>
0040 #include <rtems/score/isr.h>
0041
0042 #include <string.h> /* for memset */
0043
0044 /*
0045  *  v850 Specific Information:
0046  *
0047  *  So far nothing known to be needed at this point during initialization.
0048  */
0049 void _CPU_Initialize(void)
0050 {
0051 }
0052
0053 /*
0054  *  v850 Specific Information:
0055  *
0056  *  This method returns 0 if interrupts are enabled and 1 if they are disabled.
0057  *  The v850 only has two interrupt levels (on and off).
0058  */
0059 uint32_t _CPU_ISR_Get_level( void )
0060 {
0061   unsigned int psw;
0062
0063   v850_get_psw( psw );
0064
0065   if ( (psw & V850_PSW_INTERRUPT_DISABLE_MASK) == V850_PSW_INTERRUPT_DISABLE )
0066     return 1;
0067
0068   return 0;
0069 }
0070
0071 /*
0072  *  v850 Specific Information:
0073  *
0074  *  This method initializes a v850 context control structure.
0075  */
0076 void _CPU_Context_Initialize(
0077   Context_Control  *the_context,
0078   uint32_t         *stack_base,
0079   uint32_t          size,
0080   uint32_t          new_level,
0081   void             *entry_point,
0082   bool              is_fp,
0083   void             *tls_area
0084 )
0085 {
0086   uint32_t  stack_high;  /* highest "stack aligned" address */
0087   uint32_t  psw;         /* highest "stack aligned" address */
0088
0089   memset( the_context, 0, sizeof(Context_Control) );
0090
0091   /*
0092    *  On CPUs with stacks which grow down, we build the stack
0093    *  based on the stack_high address.
0094    */
0095   stack_high = ((uint32_t)(stack_base) + size);
0096   stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
0097
0098   v850_get_psw( psw );
0099   psw &= ~V850_PSW_INTERRUPT_DISABLE_MASK;
0100   if ( new_level )
0101     psw |= V850_PSW_INTERRUPT_DISABLE;
0102   else
0103     psw |= V850_PSW_INTERRUPT_ENABLE;
0104
0105   the_context->r31              = (uint32_t) entry_point;
0106   the_context->r3_stack_pointer = stack_high;
0107   the_context->psw              = psw;
0108
0109 #if 0
0110   printk( "the_context = %p\n",      the_context );
0111   printk( "stack base  = 0x%08x\n",  stack_base );
0112   printk( "stack size  = 0x%08x\n",  size );
0113   printk( "sp          = 0x%08x\n",  the_context->r3_stack_pointer );
0114   printk( "psw         = 0x%08x\n",  the_context->psw );
0115 #endif
0116 }
0117