rtems/score/cpuimpl.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief CPU Port Implementation API
0007  */
0008
0009 /*
0010  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef _RTEMS_SCORE_CPUIMPL_H
0035 #define _RTEMS_SCORE_CPUIMPL_H
0036
0037 #include <rtems/score/cpu.h>
0038
0039 /**
0040  * @defgroup RTEMSScoreCPUSPARC64 SPARC64
0041  *
0042  * @ingroup RTEMSScoreCPU
0043  *
0044  * @brief SPARC64 Architecture Support
0045  *
0046  * @{
0047  */
0048
0049 #define CPU_PER_CPU_CONTROL_SIZE 0
0050
0051 #define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
0052
0053 #ifndef ASM
0054
0055 #ifdef __cplusplus
0056 extern "C" {
0057 #endif
0058
0059 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
0060 {
0061   (void) pattern;
0062
0063   /* TODO */
0064 }
0065
0066 static inline void _CPU_Context_validate( uintptr_t pattern )
0067 {
0068   (void) pattern;
0069
0070   while (1) {
0071     /* TODO */
0072   }
0073 }
0074
0075 static inline void _CPU_Instruction_illegal( void )
0076 {
0077   __asm__ volatile ( "unimp" );
0078 }
0079
0080 static inline void _CPU_Instruction_no_operation( void )
0081 {
0082   __asm__ volatile ( "nop" );
0083 }
0084
0085 static inline void _CPU_Use_thread_local_storage(
0086   const Context_Control *context
0087 )
0088 {
0089   (void) context;
0090 }
0091
0092 static inline void *_CPU_Get_TLS_thread_pointer(
0093   const Context_Control *context
0094 )
0095 {
0096   (void) context;
0097   return NULL;
0098 }
0099
0100 #ifdef __cplusplus
0101 }
0102 #endif
0103
0104 #endif /* ASM */
0105
0106 #endif /* _RTEMS_SCORE_CPUIMPL_H */