cpu/sparc/sparc-exception-frame-print.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUSPARC
0007  *
0008  * @brief This source file contains the SPARC-specific implementation of
0009  *   _CPU_Exception_frame_print().
0010  */
0011
0012 /*
0013  * Copyright (C) 2021 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/cpu.h>
0042 #include <rtems/bspIo.h>
0043 #include <inttypes.h>
0044
0045 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
0046 {
0047   size_t i;
0048   size_t j;
0049   const char *desc;
0050
0051   switch ( SPARC_REAL_TRAP_NUMBER( frame->trap ) ) {
0052     case 0x01:
0053       desc = " (instruction access exception)";
0054       break;
0055     case 0x02:
0056       desc = " (illegal instruction)";
0057       break;
0058     case 0x03:
0059       desc = " (privileged instruction)";
0060       break;
0061     case 0x04:
0062       desc = " (fp disabled)";
0063       break;
0064     case 0x05:
0065       desc = " (window overflow)";
0066       break;
0067     case 0x06:
0068       desc = " (window underflow)";
0069       break;
0070     case 0x07:
0071       desc = " (memory address not aligned)";
0072       break;
0073     case 0x08:
0074       desc = " (fp exception)";
0075       break;
0076     case 0x09:
0077       desc = " (data access exception)";
0078       break;
0079     case 0x0A:
0080       desc = " (tag overflow)";
0081       break;
0082     case 0x11:
0083     case 0x12:
0084     case 0x13:
0085     case 0x14:
0086     case 0x15:
0087     case 0x16:
0088     case 0x17:
0089     case 0x18:
0090     case 0x19:
0091     case 0x1A:
0092     case 0x1B:
0093     case 0x1C:
0094     case 0x1D:
0095     case 0x1E:
0096     case 0x1F:
0097       desc = " (external interrupt)";
0098       break;
0099     case 0x24:
0100       desc = " (cp disabled)";
0101       break;
0102     case 0x28:
0103       desc = " (cp exception)";
0104       break;
0105     default:
0106       desc = "";
0107       break;
0108   }
0109
0110   printk(
0111     "\n"
0112     "unexpected trap %" PRIu32 "%s\n"
0113     "PSR = 0x%08" PRIx32 "\n"
0114     "PC = 0x%08" PRIx32 "\n"
0115     "nPC = 0x%08" PRIx32 "\n"
0116     "WIM = 0x%08" PRIx32 "\n"
0117     "Y = 0x%08" PRIx32 "\n",
0118     frame->trap,
0119     desc,
0120     frame->psr,
0121     frame->pc,
0122     frame->npc,
0123     frame->wim,
0124     frame->y
0125   );
0126
0127   for ( i = 0; i < RTEMS_ARRAY_SIZE( frame->global ); ++i ) {
0128     printk( "g%zu = 0x%08" PRIx32 "\n", i, frame->global[ i ] );
0129   }
0130
0131   for ( i = 0; i < RTEMS_ARRAY_SIZE( frame->output ); ++i ) {
0132     printk( "o%zu[CWP - 0] = 0x%08" PRIx32 "\n", i, frame->output[ i ] );
0133   }
0134
0135   for ( i = 0; i < RTEMS_ARRAY_SIZE( frame->windows ); ++i ) {
0136     const SPARC_Register_window *win;
0137
0138     win = &frame->windows[ i ];
0139
0140     for ( j = 0; j < RTEMS_ARRAY_SIZE( win->local ); ++j ) {
0141       printk( "l%zu[CWP - %zu] = 0x%08" PRIx32 "\n", j, i, win->local[ j ] );
0142     }
0143
0144     for ( j = 0; j < RTEMS_ARRAY_SIZE( win->input ); ++j ) {
0145       printk( "i%zu[CWP - %zu] = 0x%08" PRIx32 "\n", j, i, win->input[ j ] );
0146     }
0147   }
0148
0149 #if SPARC_HAS_FPU == 1
0150   printk( "FSR = 0x%08" PRIx32 "\n", frame->fsr );
0151
0152   for ( i = 0; i < RTEMS_ARRAY_SIZE( frame->fp ); ++i ) {
0153     j = i * 2;
0154     printk( "fp%zu:fp%zu = 0x%016" PRIx64 "\n", j, j + 1, frame->fp[ i ] );
0155   }
0156 #endif
0157 }