include/libcpu/grlib-tn-0018.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUSPARC
0007  *
0008  * @brief This header file provides interfaces of the GRLIB-TN-0018 LEON3FT
0009  *   RETT Restart Errata fixes.
0010  */
0011
0012 /*
0013  * Copyright (C) 2020 Cobham Gaisler AB
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 /* NOTE: the lda should be on offset 0x18 */
0038 #if defined(__FIX_LEON3FT_TN0018)
0039
0040 /* LEON3 Cache controller register accessed via ASI 2 */
0041 #define ASI_CTRL 0x02
0042 #define CCTRL_IP_BIT 15
0043 #define CCTRL_ICS 0x3
0044
0045 /*
0046  * l3: (out) original cctrl
0047  * l4: (out) original cctrl with ics=0
0048  * NOTE: This macro modifies psr.icc.
0049  */
0050 .macro TN0018_WAIT_IFLUSH out1 out2
0051 1:
0052         ! wait for pending iflush to complete
0053         lda     [%g0] ASI_CTRL, \out1
0054         srl     \out1, CCTRL_IP_BIT, \out2
0055         andcc   \out2, 1, %g0
0056         bne     1b
0057          andn   \out1, CCTRL_ICS, \out2
0058 .endm
0059
0060
0061 .macro TN0018_WRITE_PSR src
0062         wr      \src, %psr
0063 .endm
0064
0065 /* Prevent following jmp;rett sequence from "re-executing" due to cached RETT or source
0066  * registers (l1 and l2) containing bit faults triggering ECC.
0067  *
0068  * l3: (in) original cctrl
0069  * l4: (in) original cctrl with ics=0
0070  * NOTE: This macro MUST be immediately followed by the "jmp;rett" pair.
0071  */
0072 .macro TN0018_FIX in1 in2
0073         .align  0x20                    ! align the sta for performance
0074         sta     \in2, [%g0] ASI_CTRL    ! disable icache
0075         nop                             ! delay for sta to have effect on rett
0076         or      %l1, %l1, %l1           ! delay + catch rf parity error on l1
0077         or      %l2, %l2, %l2           ! delay + catch rf parity error on l2
0078         sta     \in1, [%g0] ASI_CTRL     ! re-enable icache after rett
0079         nop                             ! delay ensures insn after gets cached
0080 .endm
0081
0082 #else
0083
0084 .macro TN0018_WAIT_IFLUSH out1 out2
0085 .endm
0086
0087 .macro TN0018_WRITE_PSR src
0088 .endm
0089
0090 .macro TN0018_FIX in1 in2
0091 .endm
0092
0093 #endif
0094