Warning, /cpukit/score/cpu/sparc/README.md is written in an unsupported language. File is not indexed.
0001 SPARC
0002 =====
0003
0004 This file discusses SPARC specific issues which are important to
0005 this port. The primary topics in this file are:
0006
0007 + Global Register Usage
0008 + Stack Frame
0009 + EF bit in the PSR
0010
0011
0012 Global Register Usage
0013 ---------------------
0014
0015 This information on register usage is based heavily on a comment in the
0016 file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source.
0017
0018 + g0 is hardwired to 0
0019 + On non-v9 systems:
0020 - g1 is free to use as temporary.
0021 - g2-g4 are reserved for applications. Gcc normally uses them as
0022 temporaries, but this can be disabled via the -mno-app-regs option.
0023 - g5 through g7 are reserved for the operating system.
0024 + On v9 systems:
0025 - g1 and g5 are free to use as temporaries.
0026 - g2-g4 are reserved for applications (the compiler will not normally use
0027 them, but they can be used as temporaries with -mapp-regs).
0028 - g6-g7 are reserved for the operating system.
0029
0030 NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios:
0031
0032 + as a temporary by the 64 bit sethi pattern
0033 + when restoring call-preserved registers in large stack frames
0034
0035 RTEMS places no constraints on the usage of the global registers. Although
0036 gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the
0037 operating system, RTEMS does not assume any special use for them.
0038
0039
0040
0041 Stack Frame
0042 -----------
0043
0044 The stack grows downward (i.e. to lower addresses) on the SPARC architecture.
0045
0046 The following is the organization of the stack frame:
0047
0048 ```
0049
0050 | ............... |
0051 fp | |
0052 +-------------------------------+
0053 | |
0054 | Local registers, temporaries, |
0055 | and saved floats | x bytes
0056 | |
0057 sp + x +-------------------------------+
0058 | |
0059 | outgoing parameters past |
0060 | the sixth one | x bytes
0061 | |
0062 sp + 92 +-------------------------------+ *
0063 | | *
0064 | area for callee to save | *
0065 | register arguments | * 24 bytes
0066 | | *
0067 sp + 68 +-------------------------------+ *
0068 | | *
0069 | structure return pointer | * 4 bytes
0070 | | *
0071 sp + 64 +-------------------------------+ *
0072 | | *
0073 | local register set | * 32 bytes
0074 | | *
0075 sp + 32 +-------------------------------+ *
0076 | | *
0077 | input register set | * 32 bytes
0078 | | *
0079 sp +-------------------------------+ *
0080 ```
0081
0082 * = minimal stack frame
0083
0084 x = optional components
0085
0086 EF bit in the PSR
0087 =================
0088
0089 The EF (enable floating point unit) in the PSR is utilized in this port to
0090 prevent non-floating point tasks from performing floating point
0091 operations. This bit is maintained as part of the integer context.
0092 However, the floating point context is switched BEFORE the integer
0093 context. Thus the EF bit in place at the time of the FP switch may
0094 indicate that FP operations are disabled. This occurs on certain task
0095 switches, when the EF bit will be 0 for the outgoing task and thus a fault
0096 will be generated on the first FP operation of the FP context save.
0097
0098 The remedy for this is to enable FP access as the first step in both the
0099 save and restore of the FP context area. This bit will be subsequently
0100 reloaded by the integer context switch.
0101
0102 Two of the scenarios which demonstrate this problem are outlined below:
0103
0104 1. When the first FP task is switched to. The system tasks are not FP and
0105 thus would be unable to restore the FP context of the incoming task.
0106
0107 2. On a deferred FP context switch. In this case, the system might switch
0108 from FP Task A to non-FP Task B and then to FP Task C. In this scenario,
0109 the floating point state must technically be saved by a non-FP task.
