cpu/riscv/riscv-context-volatile-clobber.S

0001 /*
0002  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0003  * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
0004  *
0005  * Redistribution and use in source and binary forms, with or without
0006  * modification, are permitted provided that the following conditions
0007  * are met:
0008  * 1. Redistributions of source code must retain the above copyright
0009  *    notice, this list of conditions and the following disclaimer.
0010  * 2. Redistributions in binary form must reproduce the above copyright
0011  *    notice, this list of conditions and the following disclaimer in the
0012  *    documentation and/or other materials provided with the distribution.
0013  *
0014  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0015  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0016  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0017  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0018  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0019  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0020  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0021  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0022  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0023  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0024  * SUCH DAMAGE.
0025  */
0026
0027 #ifdef HAVE_CONFIG_H
0028 #include "config.h"
0029 #endif
0030
0031 #include <rtems/asm.h>
0032
0033     .section    .text, "ax", @progbits
0034     .align  2
0035
0036 PUBLIC(_CPU_Context_volatile_clobber)
0037 SYM(_CPU_Context_volatile_clobber):
0038
0039 #if __riscv_flen > 0
0040     andi    t0, a0, 0x1f
0041     fsflags t0
0042
0043     addi    t0, a0, 15
0044     FMVYX   ft0, t0
0045     addi    t0, a0, 16
0046     FMVYX   ft1, t0
0047     addi    t0, a0, 17
0048     FMVYX   ft2, t0
0049     addi    t0, a0, 18
0050     FMVYX   ft3, t0
0051     addi    t0, a0, 19
0052     FMVYX   ft4, t0
0053     addi    t0, a0, 20
0054     FMVYX   ft5, t0
0055     addi    t0, a0, 21
0056     FMVYX   ft6, t0
0057     addi    t0, a0, 22
0058     FMVYX   ft7, t0
0059     addi    t0, a0, 23
0060     FMVYX   ft8, t0
0061     addi    t0, a0, 24
0062     FMVYX   ft9, t0
0063     addi    t0, a0, 25
0064     FMVYX   ft10, t0
0065     addi    t0, a0, 26
0066     FMVYX   ft11, t0
0067     addi    t0, a0, 27
0068     FMVYX   fa0, t0
0069     addi    t0, a0, 28
0070     FMVYX   fa1, t0
0071     addi    t0, a0, 29
0072     FMVYX   fa2, t0
0073     addi    t0, a0, 30
0074     FMVYX   fa3, t0
0075     addi    t0, a0, 31
0076     FMVYX   fa4, t0
0077     addi    t0, a0, 32
0078     FMVYX   fa5, t0
0079     addi    t0, a0, 33
0080     FMVYX   fa6, t0
0081     addi    t0, a0, 34
0082     FMVYX   fa7, t0
0083 #endif /* __riscv_flen */
0084
0085     addi    a1, a0, 1
0086     addi    a2, a0, 2
0087     addi    a3, a0, 3
0088     addi    a4, a0, 4
0089     addi    a5, a0, 5
0090     addi    a6, a0, 6
0091     addi    a7, a0, 7
0092     addi    t0, a0, 8
0093     addi    t1, a0, 9
0094     addi    t2, a0, 10
0095     addi    t3, a0, 11
0096     addi    t4, a0, 12
0097     addi    t5, a0, 13
0098     addi    t6, a0, 14
0099
0100     ret