cpu/riscv/riscv-context-initialize.c

0001 /*
0002  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0003  *
0004  * Copyright (c) 2015 University of York.
0005  * Hesham Almatary <hesham@alumni.york.ac.uk>
0006  *
0007  * COPYRIGHT (c) 1989-2006.
0008  * On-Line Applications Research Corporation (OAR).
0009  *
0010  * Redistribution and use in source and binary forms, with or without
0011  * modification, are permitted provided that the following conditions
0012  * are met:
0013  * 1. Redistributions of source code must retain the above copyright
0014  *    notice, this list of conditions and the following disclaimer.
0015  * 2. Redistributions in binary form must reproduce the above copyright
0016  *    notice, this list of conditions and the following disclaimer in the
0017  *    documentation and/or other materials provided with the distribution.
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0023  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0024  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0025  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0026  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0027  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0028  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0029  * SUCH DAMAGE.
0030  */
0031
0032 #ifdef HAVE_CONFIG_H
0033 #include "config.h"
0034 #endif
0035
0036 #include <rtems/score/cpuimpl.h>
0037 #include <rtems/score/address.h>
0038 #include <rtems/score/tls.h>
0039
0040 void _CPU_Context_Initialize(
0041   Context_Control *context,
0042   void            *stack_area_begin,
0043   size_t           stack_area_size,
0044   uint32_t         new_level,
0045   void          ( *entry_point )( void ),
0046   bool             is_fp,
0047   void            *tls_area
0048 )
0049 {
0050   void *stack;
0051
0052   stack = _Addresses_Add_offset( stack_area_begin, stack_area_size );
0053   stack = _Addresses_Align_down( stack, CPU_STACK_ALIGNMENT );
0054
0055   context->ra = (uintptr_t) entry_point;
0056   context->sp = (uintptr_t) stack;
0057   context->isr_dispatch_disable = 0;
0058
0059 #if __riscv_flen > 0
0060   /*
0061    * According to C11 section 7.6 "Floating-point environment <fenv.h>" the
0062    * floating-point environment shall be initialized to the current state of
0063    * the creating thread.
0064    */
0065   context->fcsr = _RISCV_Read_FCSR();
0066 #endif
0067
0068   if ( tls_area != NULL ) {
0069     void *tls_block;
0070
0071     tls_block = _TLS_Initialize_area( tls_area );
0072     context->tp = (uintptr_t) tls_block;
0073   }
0074 }