cpu/riscv/cpu.c

0001 /*
0002  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0003  *
0004  * Copyright (c) 2015 University of York.
0005  * Hesham ALmatary <hesham@alumni.york.ac.uk>
0006  *
0007  * COPYRIGHT (c) 1989-1999.
0008  * On-Line Applications Research Corporation (OAR).
0009  *
0010  * Redistribution and use in source and binary forms, with or without
0011  * modification, are permitted provided that the following conditions
0012  * are met:
0013  * 1. Redistributions of source code must retain the above copyright
0014  *    notice, this list of conditions and the following disclaimer.
0015  * 2. Redistributions in binary form must reproduce the above copyright
0016  *    notice, this list of conditions and the following disclaimer in the
0017  *    documentation and/or other materials provided with the distribution.
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0023  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0024  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0025  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0026  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0027  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0028  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0029  * SUCH DAMAGE.
0030  */
0031
0032 #include <rtems/score/cpuimpl.h>
0033 #include <rtems/score/isr.h>
0034 #include <rtems/score/riscv-utility.h>
0035
0036 #define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \
0037   RTEMS_STATIC_ASSERT( \
0038     offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \
0039     riscv_context_offset_ ## field \
0040   )
0041
0042 RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
0043 #ifdef RTEMS_SMP
0044 RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING );
0045 #endif
0046 RISCV_ASSERT_CONTEXT_OFFSET( ra, RA );
0047 RISCV_ASSERT_CONTEXT_OFFSET( sp, SP );
0048 RISCV_ASSERT_CONTEXT_OFFSET( tp, TP );
0049 RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 );
0050 RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 );
0051 RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 );
0052 RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 );
0053 RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 );
0054 RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 );
0055 RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 );
0056 RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 );
0057 RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 );
0058 RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 );
0059 RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 );
0060 RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 );
0061
0062 #if __riscv_flen > 0
0063
0064 RISCV_ASSERT_CONTEXT_OFFSET( fcsr, FCSR );
0065 RISCV_ASSERT_CONTEXT_OFFSET( fs0, FS0 );
0066 RISCV_ASSERT_CONTEXT_OFFSET( fs1, FS1 );
0067 RISCV_ASSERT_CONTEXT_OFFSET( fs2, FS2 );
0068 RISCV_ASSERT_CONTEXT_OFFSET( fs3, FS3 );
0069 RISCV_ASSERT_CONTEXT_OFFSET( fs4, FS4 );
0070 RISCV_ASSERT_CONTEXT_OFFSET( fs5, FS5 );
0071 RISCV_ASSERT_CONTEXT_OFFSET( fs6, FS6 );
0072 RISCV_ASSERT_CONTEXT_OFFSET( fs7, FS7 );
0073 RISCV_ASSERT_CONTEXT_OFFSET( fs8, FS8 );
0074 RISCV_ASSERT_CONTEXT_OFFSET( fs9, FS9 );
0075 RISCV_ASSERT_CONTEXT_OFFSET( fs10, FS10 );
0076 RISCV_ASSERT_CONTEXT_OFFSET( fs11, FS11 );
0077
0078 #endif /* __riscv_flen */
0079
0080 #define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \
0081   RTEMS_STATIC_ASSERT( \
0082     offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \
0083     riscv_interrupt_frame_offset_ ## field \
0084   )
0085
0086 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS );
0087 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC );
0088 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 );
0089 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 );
0090 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 );
0091 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA );
0092 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 );
0093 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 );
0094 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 );
0095 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 );
0096 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 );
0097 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 );
0098 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 );
0099 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 );
0100 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 );
0101 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 );
0102 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 );
0103 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 );
0104 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 );
0105 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 );
0106
0107 #if __riscv_flen > 0
0108
0109 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fcsr, FCSR );
0110 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft0, FT0 );
0111 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft1, FT1 );
0112 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft2, FT2 );
0113 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft3, FT3 );
0114 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft4, FT4 );
0115 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft5, FT5 );
0116 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft6, FT6 );
0117 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft7, FT7 );
0118 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft8, FT8 );
0119 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft9, FT9 );
0120 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft10, FT10 );
0121 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft11, FT11 );
0122 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa0, FA0 );
0123 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa1, FA1 );
0124 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa2, FA2 );
0125 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa3, FA3 );
0126 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa4, FA4 );
0127 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa5, FA5 );
0128 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa6, FA6 );
0129 RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 );
0130
0131 #endif /* __riscv_flen */
0132
0133 #define RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( field, off ) \
0134   RTEMS_STATIC_ASSERT( \
0135     offsetof( CPU_Exception_frame, field) == RISCV_EXCEPTION_FRAME_ ## off, \
0136     riscv_context_offset_ ## field \
0137   )
0138
0139 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( mcause, MCAUSE );
0140 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( sp, SP );
0141 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( gp, GP );
0142 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( tp, TP );
0143 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s2, S2 );
0144 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s3, S3 );
0145 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s4, S4 );
0146 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s5, S5 );
0147 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s6, S6 );
0148 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s7, S7 );
0149 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s8, S8 );
0150 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s9, S9 );
0151 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s10, S10 );
0152 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s11, S11 );
0153
0154 #if __riscv_flen > 0
0155
0156 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs0, FS0 );
0157 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs1, FS1 );
0158 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs2, FS2 );
0159 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs3, FS3 );
0160 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs4, FS4 );
0161 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs5, FS5 );
0162 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs6, FS6 );
0163 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs7, FS7 );
0164 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs8, FS8 );
0165 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs9, FS9 );
0166 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs10, FS10 );
0167 RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs11, FS11 );
0168
0169 #endif /* __riscv_flen */
0170
0171 RTEMS_STATIC_ASSERT(
0172   sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0,
0173   riscv_interrupt_frame_size
0174 );
0175
0176 /**
0177  * @brief Performs processor dependent initialization.
0178  */
0179 void _CPU_Initialize(void)
0180 {
0181   /* Do nothing */
0182 }
0183
0184 uint32_t _CPU_ISR_Get_level( void )
0185 {
0186   if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
0187     return 0;
0188   }
0189
0190   return 1;
0191 }
0192
0193 void *_CPU_Thread_Idle_body( uintptr_t ignored )
0194 {
0195   while ( true ) {
0196     __asm__ volatile ( "wfi" );
0197   }
0198 }