cpu/powerpc/cpu.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  @brief PowerPC Dependent Source
0007  */
0008
0009 /*
0010  * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 /*
0035  * For now, this file is just a stub to work around
0036  * structural deficiencies of the powerpc port.
0037  */
0038
0039 #ifdef HAVE_CONFIG_H
0040 #include "config.h"
0041 #endif
0042
0043 #include <rtems/score/cpuimpl.h>
0044
0045 #define PPC_ASSERT_OFFSET(field, off) \
0046   RTEMS_STATIC_ASSERT( \
0047     offsetof(ppc_context, field) + PPC_DEFAULT_CACHE_LINE_SIZE \
0048       == PPC_CONTEXT_OFFSET_ ## off, \
0049     ppc_context_offset_ ## field \
0050   )
0051
0052 PPC_ASSERT_OFFSET(gpr1, GPR1);
0053 PPC_ASSERT_OFFSET(msr, MSR);
0054 PPC_ASSERT_OFFSET(lr, LR);
0055 PPC_ASSERT_OFFSET(cr, CR);
0056 PPC_ASSERT_OFFSET(gpr14, GPR14);
0057 PPC_ASSERT_OFFSET(gpr15, GPR15);
0058 PPC_ASSERT_OFFSET(gpr16, GPR16);
0059 PPC_ASSERT_OFFSET(gpr17, GPR17);
0060 PPC_ASSERT_OFFSET(gpr18, GPR18);
0061 PPC_ASSERT_OFFSET(gpr19, GPR19);
0062 PPC_ASSERT_OFFSET(gpr20, GPR20);
0063 PPC_ASSERT_OFFSET(gpr21, GPR21);
0064 PPC_ASSERT_OFFSET(gpr22, GPR22);
0065 PPC_ASSERT_OFFSET(gpr23, GPR23);
0066 PPC_ASSERT_OFFSET(gpr24, GPR24);
0067 PPC_ASSERT_OFFSET(gpr25, GPR25);
0068 PPC_ASSERT_OFFSET(gpr26, GPR26);
0069 PPC_ASSERT_OFFSET(gpr27, GPR27);
0070 PPC_ASSERT_OFFSET(gpr28, GPR28);
0071 PPC_ASSERT_OFFSET(gpr29, GPR29);
0072 PPC_ASSERT_OFFSET(gpr30, GPR30);
0073 PPC_ASSERT_OFFSET(gpr31, GPR31);
0074 PPC_ASSERT_OFFSET(tp, TP);
0075 PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
0076
0077 #ifdef RTEMS_SMP
0078   PPC_ASSERT_OFFSET(is_executing, IS_EXECUTING);
0079 #endif
0080
0081 #ifdef PPC_MULTILIB_ALTIVEC
0082   PPC_ASSERT_OFFSET(vrsave, VRSAVE);
0083   PPC_ASSERT_OFFSET(vscr, VSCR);
0084   RTEMS_STATIC_ASSERT(
0085     PPC_CONTEXT_OFFSET_V20 % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
0086     ppc_context_altivec
0087   );
0088   PPC_ASSERT_OFFSET(v20, V20);
0089   PPC_ASSERT_OFFSET(v21, V21);
0090   PPC_ASSERT_OFFSET(v22, V22);
0091   PPC_ASSERT_OFFSET(v23, V23);
0092   PPC_ASSERT_OFFSET(v24, V24);
0093   PPC_ASSERT_OFFSET(v25, V25);
0094   PPC_ASSERT_OFFSET(v26, V26);
0095   PPC_ASSERT_OFFSET(v27, V27);
0096   PPC_ASSERT_OFFSET(v28, V28);
0097   PPC_ASSERT_OFFSET(v29, V29);
0098   PPC_ASSERT_OFFSET(v30, V30);
0099   PPC_ASSERT_OFFSET(v31, V31);
0100 #endif
0101
0102 #ifdef PPC_MULTILIB_FPU
0103   PPC_ASSERT_OFFSET(f14, F14);
0104   PPC_ASSERT_OFFSET(f15, F15);
0105   PPC_ASSERT_OFFSET(f16, F16);
0106   PPC_ASSERT_OFFSET(f17, F17);
0107   PPC_ASSERT_OFFSET(f18, F18);
0108   PPC_ASSERT_OFFSET(f19, F19);
0109   PPC_ASSERT_OFFSET(f20, F20);
0110   PPC_ASSERT_OFFSET(f21, F21);
0111   PPC_ASSERT_OFFSET(f22, F22);
0112   PPC_ASSERT_OFFSET(f23, F23);
0113   PPC_ASSERT_OFFSET(f24, F24);
0114   PPC_ASSERT_OFFSET(f25, F25);
0115   PPC_ASSERT_OFFSET(f26, F26);
0116   PPC_ASSERT_OFFSET(f27, F27);
0117   PPC_ASSERT_OFFSET(f28, F28);
0118   PPC_ASSERT_OFFSET(f29, F29);
0119   PPC_ASSERT_OFFSET(f30, F30);
0120   PPC_ASSERT_OFFSET(f31, F31);
0121 #endif
0122
0123 RTEMS_STATIC_ASSERT(
0124   sizeof(Context_Control) % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
0125   ppc_context_size
0126 );
0127
0128 #define PPC_EXC_ASSERT_OFFSET(field, off) \
0129   RTEMS_STATIC_ASSERT( \
0130     offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \
0131     CPU_Exception_frame_offset_ ## field \
0132   )
0133
0134 #define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
0135   PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
0136
0137 #define PPC_EXC_MIN_ASSERT_OFFSET(field, off) \
0138   RTEMS_STATIC_ASSERT( \
0139     offsetof(CPU_Interrupt_frame, field) == off, \
0140     CPU_Interrupt_frame_offset_ ## field \
0141   )
0142
0143 #define PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(field) \
0144   PPC_EXC_MIN_ASSERT_OFFSET(field, field ## _OFFSET)
0145
0146 PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
0147 PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
0148 PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
0149 PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
0150 PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
0151 PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
0152 PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
0153 #ifdef __SPE__
0154   PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
0155   PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
0156 #endif
0157 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
0158 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
0159 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
0160 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
0161 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
0162 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
0163 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
0164 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
0165 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
0166 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
0167 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
0168 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
0169 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
0170 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
0171 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
0172 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
0173 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
0174 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
0175 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
0176 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
0177 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
0178 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
0179 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
0180 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
0181 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
0182 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
0183 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
0184 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
0185 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
0186 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
0187 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
0188 PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
0189
0190 PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
0191 PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
0192 PPC_EXC_MIN_ASSERT_OFFSET(
0193   EXC_INTERRUPT_ENTRY_INSTANT,
0194   PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET
0195 );
0196 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CR);
0197 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CTR);
0198 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_XER);
0199 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_LR);
0200 PPC_EXC_MIN_ASSERT_OFFSET(EXC_INTERRUPT_FRAME, PPC_EXC_INTERRUPT_FRAME_OFFSET);
0201 #ifdef __SPE__
0202   PPC_EXC_MIN_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
0203   PPC_EXC_MIN_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
0204 #endif
0205 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR0);
0206 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR1);
0207 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR2);
0208 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR3);
0209 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR4);
0210 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR5);
0211 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR6);
0212 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR7);
0213 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR8);
0214 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR9);
0215 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR10);
0216 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR11);
0217 PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR12);
0218
0219 #ifdef PPC_MULTILIB_ALTIVEC
0220 PPC_EXC_ASSERT_OFFSET(VSCR, PPC_EXC_VSCR_OFFSET);
0221 PPC_EXC_ASSERT_OFFSET(VRSAVE, PPC_EXC_VRSAVE_OFFSET);
0222 RTEMS_STATIC_ASSERT(PPC_EXC_VR_OFFSET(0) % 16 == 0, PPC_EXC_VR_OFFSET);
0223 PPC_EXC_ASSERT_OFFSET(V0, PPC_EXC_VR_OFFSET(0));
0224 PPC_EXC_ASSERT_OFFSET(V1, PPC_EXC_VR_OFFSET(1));
0225 PPC_EXC_ASSERT_OFFSET(V2, PPC_EXC_VR_OFFSET(2));
0226 PPC_EXC_ASSERT_OFFSET(V3, PPC_EXC_VR_OFFSET(3));
0227 PPC_EXC_ASSERT_OFFSET(V4, PPC_EXC_VR_OFFSET(4));
0228 PPC_EXC_ASSERT_OFFSET(V5, PPC_EXC_VR_OFFSET(5));
0229 PPC_EXC_ASSERT_OFFSET(V6, PPC_EXC_VR_OFFSET(6));
0230 PPC_EXC_ASSERT_OFFSET(V7, PPC_EXC_VR_OFFSET(7));
0231 PPC_EXC_ASSERT_OFFSET(V8, PPC_EXC_VR_OFFSET(8));
0232 PPC_EXC_ASSERT_OFFSET(V9, PPC_EXC_VR_OFFSET(9));
0233 PPC_EXC_ASSERT_OFFSET(V10, PPC_EXC_VR_OFFSET(10));
0234 PPC_EXC_ASSERT_OFFSET(V11, PPC_EXC_VR_OFFSET(11));
0235 PPC_EXC_ASSERT_OFFSET(V12, PPC_EXC_VR_OFFSET(12));
0236 PPC_EXC_ASSERT_OFFSET(V13, PPC_EXC_VR_OFFSET(13));
0237 PPC_EXC_ASSERT_OFFSET(V14, PPC_EXC_VR_OFFSET(14));
0238 PPC_EXC_ASSERT_OFFSET(V15, PPC_EXC_VR_OFFSET(15));
0239 PPC_EXC_ASSERT_OFFSET(V16, PPC_EXC_VR_OFFSET(16));
0240 PPC_EXC_ASSERT_OFFSET(V17, PPC_EXC_VR_OFFSET(17));
0241 PPC_EXC_ASSERT_OFFSET(V18, PPC_EXC_VR_OFFSET(18));
0242 PPC_EXC_ASSERT_OFFSET(V19, PPC_EXC_VR_OFFSET(19));
0243 PPC_EXC_ASSERT_OFFSET(V20, PPC_EXC_VR_OFFSET(20));
0244 PPC_EXC_ASSERT_OFFSET(V21, PPC_EXC_VR_OFFSET(21));
0245 PPC_EXC_ASSERT_OFFSET(V22, PPC_EXC_VR_OFFSET(22));
0246 PPC_EXC_ASSERT_OFFSET(V23, PPC_EXC_VR_OFFSET(23));
0247 PPC_EXC_ASSERT_OFFSET(V24, PPC_EXC_VR_OFFSET(24));
0248 PPC_EXC_ASSERT_OFFSET(V25, PPC_EXC_VR_OFFSET(25));
0249 PPC_EXC_ASSERT_OFFSET(V26, PPC_EXC_VR_OFFSET(26));
0250 PPC_EXC_ASSERT_OFFSET(V27, PPC_EXC_VR_OFFSET(27));
0251 PPC_EXC_ASSERT_OFFSET(V28, PPC_EXC_VR_OFFSET(28));
0252 PPC_EXC_ASSERT_OFFSET(V29, PPC_EXC_VR_OFFSET(29));
0253 PPC_EXC_ASSERT_OFFSET(V30, PPC_EXC_VR_OFFSET(30));
0254 PPC_EXC_ASSERT_OFFSET(V31, PPC_EXC_VR_OFFSET(31));
0255
0256 PPC_EXC_MIN_ASSERT_OFFSET(VSCR, PPC_EXC_MIN_VSCR_OFFSET);
0257 RTEMS_STATIC_ASSERT(PPC_EXC_MIN_VR_OFFSET(0) % 16 == 0, PPC_EXC_MIN_VR_OFFSET);
0258 PPC_EXC_MIN_ASSERT_OFFSET(V0, PPC_EXC_MIN_VR_OFFSET(0));
0259 PPC_EXC_MIN_ASSERT_OFFSET(V1, PPC_EXC_MIN_VR_OFFSET(1));
0260 PPC_EXC_MIN_ASSERT_OFFSET(V2, PPC_EXC_MIN_VR_OFFSET(2));
0261 PPC_EXC_MIN_ASSERT_OFFSET(V3, PPC_EXC_MIN_VR_OFFSET(3));
0262 PPC_EXC_MIN_ASSERT_OFFSET(V4, PPC_EXC_MIN_VR_OFFSET(4));
0263 PPC_EXC_MIN_ASSERT_OFFSET(V5, PPC_EXC_MIN_VR_OFFSET(5));
0264 PPC_EXC_MIN_ASSERT_OFFSET(V6, PPC_EXC_MIN_VR_OFFSET(6));
0265 PPC_EXC_MIN_ASSERT_OFFSET(V7, PPC_EXC_MIN_VR_OFFSET(7));
0266 PPC_EXC_MIN_ASSERT_OFFSET(V8, PPC_EXC_MIN_VR_OFFSET(8));
0267 PPC_EXC_MIN_ASSERT_OFFSET(V9, PPC_EXC_MIN_VR_OFFSET(9));
0268 PPC_EXC_MIN_ASSERT_OFFSET(V10, PPC_EXC_MIN_VR_OFFSET(10));
0269 PPC_EXC_MIN_ASSERT_OFFSET(V11, PPC_EXC_MIN_VR_OFFSET(11));
0270 PPC_EXC_MIN_ASSERT_OFFSET(V12, PPC_EXC_MIN_VR_OFFSET(12));
0271 PPC_EXC_MIN_ASSERT_OFFSET(V13, PPC_EXC_MIN_VR_OFFSET(13));
0272 PPC_EXC_MIN_ASSERT_OFFSET(V14, PPC_EXC_MIN_VR_OFFSET(14));
0273 PPC_EXC_MIN_ASSERT_OFFSET(V15, PPC_EXC_MIN_VR_OFFSET(15));
0274 PPC_EXC_MIN_ASSERT_OFFSET(V16, PPC_EXC_MIN_VR_OFFSET(16));
0275 PPC_EXC_MIN_ASSERT_OFFSET(V17, PPC_EXC_MIN_VR_OFFSET(17));
0276 PPC_EXC_MIN_ASSERT_OFFSET(V18, PPC_EXC_MIN_VR_OFFSET(18));
0277 PPC_EXC_MIN_ASSERT_OFFSET(V19, PPC_EXC_MIN_VR_OFFSET(19));
0278 #endif
0279
0280 #ifdef PPC_MULTILIB_FPU
0281 RTEMS_STATIC_ASSERT(PPC_EXC_FR_OFFSET(0) % 8 == 0, PPC_EXC_FR_OFFSET);
0282 PPC_EXC_ASSERT_OFFSET(F0, PPC_EXC_FR_OFFSET(0));
0283 PPC_EXC_ASSERT_OFFSET(F1, PPC_EXC_FR_OFFSET(1));
0284 PPC_EXC_ASSERT_OFFSET(F2, PPC_EXC_FR_OFFSET(2));
0285 PPC_EXC_ASSERT_OFFSET(F3, PPC_EXC_FR_OFFSET(3));
0286 PPC_EXC_ASSERT_OFFSET(F4, PPC_EXC_FR_OFFSET(4));
0287 PPC_EXC_ASSERT_OFFSET(F5, PPC_EXC_FR_OFFSET(5));
0288 PPC_EXC_ASSERT_OFFSET(F6, PPC_EXC_FR_OFFSET(6));
0289 PPC_EXC_ASSERT_OFFSET(F7, PPC_EXC_FR_OFFSET(7));
0290 PPC_EXC_ASSERT_OFFSET(F8, PPC_EXC_FR_OFFSET(8));
0291 PPC_EXC_ASSERT_OFFSET(F9, PPC_EXC_FR_OFFSET(9));
0292 PPC_EXC_ASSERT_OFFSET(F10, PPC_EXC_FR_OFFSET(10));
0293 PPC_EXC_ASSERT_OFFSET(F11, PPC_EXC_FR_OFFSET(11));
0294 PPC_EXC_ASSERT_OFFSET(F12, PPC_EXC_FR_OFFSET(12));
0295 PPC_EXC_ASSERT_OFFSET(F13, PPC_EXC_FR_OFFSET(13));
0296 PPC_EXC_ASSERT_OFFSET(F14, PPC_EXC_FR_OFFSET(14));
0297 PPC_EXC_ASSERT_OFFSET(F15, PPC_EXC_FR_OFFSET(15));
0298 PPC_EXC_ASSERT_OFFSET(F16, PPC_EXC_FR_OFFSET(16));
0299 PPC_EXC_ASSERT_OFFSET(F17, PPC_EXC_FR_OFFSET(17));
0300 PPC_EXC_ASSERT_OFFSET(F18, PPC_EXC_FR_OFFSET(18));
0301 PPC_EXC_ASSERT_OFFSET(F19, PPC_EXC_FR_OFFSET(19));
0302 PPC_EXC_ASSERT_OFFSET(F20, PPC_EXC_FR_OFFSET(20));
0303 PPC_EXC_ASSERT_OFFSET(F21, PPC_EXC_FR_OFFSET(21));
0304 PPC_EXC_ASSERT_OFFSET(F22, PPC_EXC_FR_OFFSET(22));
0305 PPC_EXC_ASSERT_OFFSET(F23, PPC_EXC_FR_OFFSET(23));
0306 PPC_EXC_ASSERT_OFFSET(F24, PPC_EXC_FR_OFFSET(24));
0307 PPC_EXC_ASSERT_OFFSET(F25, PPC_EXC_FR_OFFSET(25));
0308 PPC_EXC_ASSERT_OFFSET(F26, PPC_EXC_FR_OFFSET(26));
0309 PPC_EXC_ASSERT_OFFSET(F27, PPC_EXC_FR_OFFSET(27));
0310 PPC_EXC_ASSERT_OFFSET(F28, PPC_EXC_FR_OFFSET(28));
0311 PPC_EXC_ASSERT_OFFSET(F29, PPC_EXC_FR_OFFSET(29));
0312 PPC_EXC_ASSERT_OFFSET(F30, PPC_EXC_FR_OFFSET(30));
0313 PPC_EXC_ASSERT_OFFSET(F31, PPC_EXC_FR_OFFSET(31));
0314 PPC_EXC_ASSERT_OFFSET(FPSCR, PPC_EXC_FPSCR_OFFSET);
0315
0316 RTEMS_STATIC_ASSERT(PPC_EXC_MIN_FR_OFFSET(0) % 8 == 0, PPC_EXC_MIN_FR_OFFSET);
0317 PPC_EXC_MIN_ASSERT_OFFSET(F0, PPC_EXC_MIN_FR_OFFSET(0));
0318 PPC_EXC_MIN_ASSERT_OFFSET(F1, PPC_EXC_MIN_FR_OFFSET(1));
0319 PPC_EXC_MIN_ASSERT_OFFSET(F2, PPC_EXC_MIN_FR_OFFSET(2));
0320 PPC_EXC_MIN_ASSERT_OFFSET(F3, PPC_EXC_MIN_FR_OFFSET(3));
0321 PPC_EXC_MIN_ASSERT_OFFSET(F4, PPC_EXC_MIN_FR_OFFSET(4));
0322 PPC_EXC_MIN_ASSERT_OFFSET(F5, PPC_EXC_MIN_FR_OFFSET(5));
0323 PPC_EXC_MIN_ASSERT_OFFSET(F6, PPC_EXC_MIN_FR_OFFSET(6));
0324 PPC_EXC_MIN_ASSERT_OFFSET(F7, PPC_EXC_MIN_FR_OFFSET(7));
0325 PPC_EXC_MIN_ASSERT_OFFSET(F8, PPC_EXC_MIN_FR_OFFSET(8));
0326 PPC_EXC_MIN_ASSERT_OFFSET(F9, PPC_EXC_MIN_FR_OFFSET(9));
0327 PPC_EXC_MIN_ASSERT_OFFSET(F10, PPC_EXC_MIN_FR_OFFSET(10));
0328 PPC_EXC_MIN_ASSERT_OFFSET(F11, PPC_EXC_MIN_FR_OFFSET(11));
0329 PPC_EXC_MIN_ASSERT_OFFSET(F12, PPC_EXC_MIN_FR_OFFSET(12));
0330 PPC_EXC_MIN_ASSERT_OFFSET(F13, PPC_EXC_MIN_FR_OFFSET(13));
0331 PPC_EXC_MIN_ASSERT_OFFSET(FPSCR, PPC_EXC_MIN_FPSCR_OFFSET);
0332 #endif
0333
0334 RTEMS_STATIC_ASSERT(
0335   CPU_INTERRUPT_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
0336   CPU_INTERRUPT_FRAME_SIZE
0337 );
0338
0339 RTEMS_STATIC_ASSERT(
0340   PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
0341   PPC_EXC_FRAME_SIZE
0342 );
0343
0344 RTEMS_STATIC_ASSERT(
0345   sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
0346   CPU_Exception_frame
0347 );