cpu/or1k/or1k-context-switch.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifdef HAVE_CONFIG_H
0029 #include "config.h"
0030 #endif
0031
0032 #include <rtems/asm.h>
0033 #include "rtems/score/or1k-utility.h"
0034
0035 .text
0036 .align 4
0037
0038 PUBLIC(_CPU_Context_switch)
0039 PUBLIC(_CPU_Context_restore)
0040 PUBLIC(_CPU_Context_restore_fp)
0041 PUBLIC(_CPU_Context_save_fp)
0042
0043 SYM(_CPU_Context_switch):
0044   l.sw  0(r3),r1
0045   l.sw  4(r3),r2
0046   l.sw  8(r3),r3
0047   l.sw  12(r3),r4
0048   l.sw  16(r3),r5
0049   l.sw  20(r3),r6
0050   l.sw  24(r3),r7
0051   l.sw  28(r3),r8
0052   l.sw  32(r3),r9
0053   /* Skip r10 as it's preserved to be used by TLS */
0054   /* The following set if registers are preserved across function calls */
0055   l.sw  52(r3),r14
0056   l.sw  60(r3),r16
0057   l.sw  68(r3),r18
0058   l.sw  76(r3),r20
0059   l.sw  84(r3),r22
0060   l.sw  92(r3),r24
0061   l.sw  100(r3),r26
0062   l.sw  108(r3),r28
0063   l.sw  116(r3),r30
0064
0065   /* Supervision Register */
0066   l.mfspr r13,r0, CPU_OR1K_SPR_SR
0067   l.sw  124(r3),r13
0068
0069   /* EPCR */
0070   l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
0071   l.sw  128(r3), r13 /* epcr */
0072
0073   /* EEAR */
0074   l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
0075   l.sw  132(r3), r13 /* eear */
0076
0077   /* ESR */
0078   l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
0079   l.sw  136(r3), r13  /* esr */
0080
0081 SYM(restore):
0082   l.lwz   r13,124(r4)
0083   l.mtspr r0,r13, CPU_OR1K_SPR_SR
0084
0085   /* Exception level related registers */
0086
0087   /* EPCR */
0088   l.lwz  r13,  128(r4)
0089   l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
0090
0091   /* EEAR */
0092   l.lwz  r13,  132(r4)
0093   l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
0094
0095   /* ESR */
0096   l.lwz  r13,  136(r4)
0097   l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
0098
0099   l.lwz  r1,0(r4)
0100   l.lwz  r2,4(r4)
0101   l.lwz  r3,8(r4)
0102   /* Skip r4 as it contains the current buffer address */
0103   l.lwz  r5,16(r4)
0104   l.lwz  r6,20(r4)
0105   l.lwz  r7,24(r4)
0106   l.lwz  r8,28(r4)
0107   l.lwz  r9,32(r4)
0108   l.lwz  r14,52(r4)
0109   l.lwz  r16,60(r4)
0110   l.lwz  r18,68(r4)
0111   l.lwz  r20,76(r4)
0112   l.lwz  r22,84(r4)
0113   l.lwz  r24,92(r4)
0114   l.lwz  r26,100(r4)
0115   l.lwz  r28,108(r4)
0116   l.lwz  r30,116(r4)
0117
0118   l.lwz  r4,12(r4)
0119
0120   l.jr   r9
0121   l.nop
0122
0123  SYM(_CPU_Context_restore):
0124   l.add   r4,r3,r0
0125   l.add   r13,r0,r0
0126   l.j     restore
0127   l.nop
0128
0129  SYM(_CPU_Context_restore_fp):
0130   l.nop
0131
0132  SYM(_CPU_Context_save_fp):
0133   l.nop