cpu/or1k/cpu.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  Opencore OR1K CPU Dependent Source
0005  *
0006  *  COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
0007  *  COPYRIGHT (c) 1989-1999.
0008  *  On-Line Applications Research Corporation (OAR).
0009  *
0010  * Redistribution and use in source and binary forms, with or without
0011  * modification, are permitted provided that the following conditions
0012  * are met:
0013  * 1. Redistributions of source code must retain the above copyright
0014  *    notice, this list of conditions and the following disclaimer.
0015  * 2. Redistributions in binary form must reproduce the above copyright
0016  *    notice, this list of conditions and the following disclaimer in the
0017  *    documentation and/or other materials provided with the distribution.
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0020  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0023  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0024  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0025  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0026  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0027  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0028  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0029  * POSSIBILITY OF SUCH DAMAGE.
0030  *
0031  */
0032
0033 #include <rtems/score/cpuimpl.h>
0034 #include <rtems/score/isr.h>
0035
0036 /* bsp_start_vector_table_begin is the start address of the vector table
0037  * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
0038  * and may differ from one BSP to another.
0039  */
0040 extern char bsp_start_vector_table_begin[];
0041
0042 /**
0043  * @brief Performs processor dependent initialization.
0044  */
0045 void _CPU_Initialize(void)
0046 {
0047   /* Do nothing */
0048 }
0049
0050 /* end of Fatal Error manager macros */
0051
0052 /**
0053  * @brief Sets the hardware interrupt level by the level value.
0054  *
0055  * @param[in] level for or1k can only range over two values:
0056  * 0 (enable interrupts) and 1 (disable interrupts). In future
0057  * implementations if fast context switch is implemented, the level
0058  * can range from 0 to 15. @see OpenRISC architecture manual.
0059  *
0060  */
0061 void _CPU_ISR_Set_level(uint32_t level)
0062 {
0063   uint32_t sr = 0;
0064   level = (level > 0)? 1 : 0;
0065
0066   /* map level bit to or1k interrupt enable/disable bit in sr register */
0067   level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
0068
0069   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
0070
0071   if (level == 0){ /* Enable all interrupts */
0072     sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
0073
0074   } else{
0075     sr &= ~CPU_OR1K_SPR_SR_IEE;
0076   }
0077
0078   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
0079  }
0080
0081 uint32_t  _CPU_ISR_Get_level( void )
0082 {
0083   uint32_t sr = 0;
0084
0085   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
0086
0087   return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
0088 }
0089
0090 void _CPU_ISR_install_raw_handler(
0091   uint32_t             vector,
0092   CPU_ISR_raw_handler  new_handler,
0093   CPU_ISR_raw_handler *old_handler
0094 )
0095 {
0096    CPU_ISR_raw_handler *table =
0097      (CPU_ISR_raw_handler *) bsp_start_vector_table_begin;
0098    CPU_ISR_raw_handler current_handler;
0099
0100    ISR_Level level;
0101
0102   _ISR_Local_disable( level );
0103
0104   current_handler = table [vector];
0105
0106   /* The current handler is now the old one */
0107   if (old_handler != NULL) {
0108     *old_handler = current_handler;
0109   }
0110
0111   /* Write only if necessary to avoid writes to a maybe read-only memory */
0112   if (current_handler != new_handler) {
0113     table [vector] = new_handler;
0114   }
0115
0116    _ISR_Local_enable( level );
0117 }
0118
0119 void *_CPU_Thread_Idle_body( uintptr_t ignored )
0120 {
0121   do {
0122      _OR1K_CPU_Sleep();
0123   } while (1);
0124 }