cpu/no_cpu/cpu_asm.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  @brief No CPU Assembly File
0007  */
0008
0009 /*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
0010  *
0011  *  This file contains the basic algorithms for all assembly code used
0012  *  in an specific CPU port of RTEMS.  These algorithms must be implemented
0013  *  in assembly language
0014  *
0015  *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
0016  *
0017  *  COPYRIGHT (c) 1989-1999.
0018  *  On-Line Applications Research Corporation (OAR).
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 /*
0043  *  This is supposed to be an assembly file.  This means that system.h
0044  *  and cpu.h should not be included in a "real" cpu_asm file.  An
0045  *  implementation in assembly should include "cpu_asm.h>
0046  */
0047
0048 #ifdef HAVE_CONFIG_H
0049 #include "config.h"
0050 #endif
0051
0052 #include <rtems/score/cpu.h>
0053 /* #include "cpu_asm.h> */
0054
0055 /*
0056  *  _CPU_Context_save_fp_context
0057  *
0058  *  This routine is responsible for saving the FP context
0059  *  at *fp_context_ptr.  If the point to load the FP context
0060  *  from is changed then the pointer is modified by this routine.
0061  *
0062  *  Sometimes a macro implementation of this is in cpu.h which dereferences
0063  *  the ** and a similarly named routine in this file is passed something
0064  *  like a (Context_Control_fp *).  The general rule on making this decision
0065  *  is to avoid writing assembly language.
0066  *
0067  *  NO_CPU Specific Information:
0068  *
0069  *  XXX document implementation including references if appropriate
0070  */
0071
0072 void _CPU_Context_save_fp(
0073   Context_Control_fp **fp_context_ptr
0074 )
0075 {
0076 }
0077
0078 /*
0079  *  _CPU_Context_restore_fp_context
0080  *
0081  *  This routine is responsible for restoring the FP context
0082  *  at *fp_context_ptr.  If the point to load the FP context
0083  *  from is changed then the pointer is modified by this routine.
0084  *
0085  *  Sometimes a macro implementation of this is in cpu.h which dereferences
0086  *  the ** and a similarly named routine in this file is passed something
0087  *  like a (Context_Control_fp *).  The general rule on making this decision
0088  *  is to avoid writing assembly language.
0089  *
0090  *  NO_CPU Specific Information:
0091  *
0092  *  XXX document implementation including references if appropriate
0093  */
0094
0095 void _CPU_Context_restore_fp(
0096   Context_Control_fp **fp_context_ptr
0097 )
0098 {
0099 }
0100
0101 /*  _CPU_Context_switch
0102  *
0103  *  This routine performs a normal non-FP context switch.
0104  *
0105  *  NO_CPU Specific Information:
0106  *
0107  *  XXX document implementation including references if appropriate
0108  */
0109
0110 void _CPU_Context_switch(
0111   Context_Control  *run,
0112   Context_Control  *heir
0113 )
0114 {
0115 }
0116
0117 /*
0118  *  _CPU_Context_restore
0119  *
0120  *  This routine is generally used only to restart self in an
0121  *  efficient manner.  It may simply be a label in _CPU_Context_switch.
0122  *
0123  *  NOTE: May be unnecessary to reload some registers.
0124  *
0125  *  NO_CPU Specific Information:
0126  *
0127  *  XXX document implementation including references if appropriate
0128  */
0129
0130 void _CPU_Context_restore(
0131   Context_Control *new_context
0132 )
0133 {
0134 }
0135
0136 /*  void __ISR_Handler()
0137  *
0138  *  This routine provides the RTEMS interrupt management.
0139  *
0140  *  NO_CPU Specific Information:
0141  *
0142  *  XXX document implementation including references if appropriate
0143  */
0144
0145 void _ISR_Handler(void)
0146 {
0147    /*
0148     *  This discussion ignores a lot of the ugly details in a real
0149     *  implementation such as saving enough registers/state to be
0150     *  able to do something real.  Keep in mind that the goal is
0151     *  to invoke a user's ISR handler which is written in C and
0152     *  uses a certain set of registers.
0153     *
0154     *  Also note that the exact order is to a large extent flexible.
0155     *  Hardware will dictate a sequence for a certain subset of
0156     *  _ISR_Handler while requirements for setting
0157     */
0158
0159   /*
0160    *  At entry to "common" _ISR_Handler, the vector number must be
0161    *  available.  On some CPUs the hardware puts either the vector
0162    *  number or the offset into the vector table for this ISR in a
0163    *  known place.  If the hardware does not give us this information,
0164    *  then the assembly portion of RTEMS for this port will contain
0165    *  a set of distinct interrupt entry points which somehow place
0166    *  the vector number in a known place (which is safe if another
0167    *  interrupt nests this one) and branches to _ISR_Handler.
0168    *
0169    *  save some or all context on stack
0170    *  may need to save some special interrupt information for exit
0171    *
0172    *  if ( _ISR_Nest_level == 0 )
0173    *    switch to software interrupt stack
0174    *
0175    *  _ISR_Nest_level++;
0176    *
0177    *  _Thread_Dispatch_disable_level++;
0178    *
0179    *  (*_ISR_Vector_table[ vector ])( vector );
0180    *
0181    *  _Thread_Dispatch_disable_level--;
0182    *
0183    *  --_ISR_Nest_level;
0184    *
0185    *  if ( _ISR_Nest_level )
0186    *    goto the label "exit interrupt (simple case)"
0187    *
0188    *  if ( _Thread_Dispatch_disable_level )
0189    *    goto the label "exit interrupt (simple case)"
0190    *
0191    *  if ( _Thread_Dispatch_necessary ) {
0192    *    call _Thread_Dispatch() or prepare to return from interrupt
0193    *    prepare to get out of interrupt
0194    *    return from interrupt
0195    *
0196    *  LABEL "exit interrupt (simple case):
0197    *  if outermost interrupt
0198    *    restore stack
0199    *  prepare to get out of interrupt
0200    *  return from interrupt
0201    */
0202 }