cpu/nios2/nios2-isr-set-level.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief NIOS2 ISR Set Level
0007  */
0008
0009 /*
0010  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0011  *
0012  * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
0013  *
0014  * COPYRIGHT (c) 1989-2006
0015  * On-Line Applications Research Corporation (OAR).
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions
0019  * are met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0027  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0028  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0029  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0030  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0031  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0032  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0033  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0034  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0035  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0036  * POSSIBILITY OF SUCH DAMAGE.
0037  */
0038
0039 #ifdef HAVE_CONFIG_H
0040 #include "config.h"
0041 #endif
0042
0043 #include <rtems/score/cpu.h>
0044 #include <rtems/score/interr.h>
0045 #include <rtems/score/nios2-utility.h>
0046
0047 uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status )
0048 {
0049   switch ( _Nios2_ISR_Get_status_mask() ) {
0050     case NIOS2_ISR_STATUS_MASK_IIC:
0051       if ( new_level == 0 ) {
0052         status |= NIOS2_STATUS_PIE;
0053       } else {
0054         status &= ~NIOS2_STATUS_PIE;
0055       }
0056       break;
0057     case NIOS2_ISR_STATUS_MASK_EIC_IL:
0058       status &= ~NIOS2_STATUS_IL_MASK;
0059       status |= (new_level << NIOS2_STATUS_IL_OFFSET) & NIOS2_STATUS_IL_MASK;
0060       break;
0061     case NIOS2_ISR_STATUS_MASK_EIC_RSIE:
0062       if ( new_level == 0 ) {
0063         status |= NIOS2_STATUS_RSIE;
0064       } else {
0065         status &= ~NIOS2_STATUS_RSIE;
0066       }
0067       break;
0068     default:
0069       /* FIXME */
0070       _Terminate( INTERNAL_ERROR_CORE, 0xdeadbeef );
0071       break;
0072   }
0073
0074   return status;
0075 }
0076
0077 void _CPU_ISR_Set_level( uint32_t new_level )
0078 {
0079   uint32_t status = _Nios2_Get_ctlreg_status();
0080
0081   status = _Nios2_ISR_Set_level( new_level, status );
0082
0083   _Nios2_Set_ctlreg_status( status );
0084 }