cpu/moxie/cpu.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  Moxie CPU Dependent Source
0005  *
0006  *  COPYRIGHT (c) 2011 Anthony Green
0007  *
0008  *  Based on example code and other ports with this copyright:
0009  *
0010  *  COPYRIGHT (c) 1989-1999, 2010.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifdef HAVE_CONFIG_H
0036 #include "config.h"
0037 #endif
0038
0039 #include <rtems/score/cpuimpl.h>
0040 #include <rtems/score/isr.h>
0041 #include <rtems/bspIo.h>
0042
0043 /*  _CPU_Initialize
0044  *
0045  *  This routine performs processor dependent initialization.
0046  *
0047  *  INPUT PARAMETERS: NONE
0048  */
0049 void _CPU_Initialize(void)
0050 {
0051   /*
0052    *  If there is not an easy way to initialize the FP context
0053    *  during Context_Initialize, then it is usually easier to
0054    *  save an "uninitialized" FP context here and copy it to
0055    *  the task's during Context_Initialize.
0056    */
0057
0058   /* FP context initialization support goes here */
0059 }
0060
0061 /*
0062  *  _CPU_ISR_Get_level
0063  *
0064  *  This routine returns the current interrupt level.
0065  */
0066 uint32_t   _CPU_ISR_Get_level( void )
0067 {
0068   return 0;
0069 }
0070
0071 void _CPU_ISR_install_vector(
0072   uint32_t         vector,
0073   CPU_ISR_handler  new_handler,
0074   CPU_ISR_handler *old_handler
0075 )
0076 {
0077   *old_handler = _ISR_Vector_table[ vector ];
0078   _ISR_Vector_table[ vector ] = new_handler;
0079 }
0080
0081 /*
0082  *  _CPU_Thread_Idle_body
0083  *
0084  *  NOTES:
0085  *
0086  *  1. This is the same as the regular CPU independent algorithm.
0087  *
0088  *  2. If you implement this using a "halt", "idle", or "shutdown"
0089  *     instruction, then don't forget to put it in an infinite loop.
0090  *
0091  *  3. Be warned. Some processors with onboard DMA have been known
0092  *     to stop the DMA if the CPU were put in IDLE mode.  This might
0093  *     also be a problem with other on-chip peripherals.  So use this
0094  *     hook with caution.
0095  */
0096 #if 0
0097 void *_CPU_Thread_Idle_body( uintptr_t ignored )
0098 {
0099
0100   for( ; ; )
0101     IDLE_Monitor();
0102         /*asm(" sleep   \n"); */
0103     /* insert your "halt" instruction here */ ;
0104 }
0105 #endif