cpu/microblaze/microblaze-context-switch.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUMicroBlaze
0007  *
0008  * @brief MicroBlaze context switch implementation
0009  */
0010
0011 /*
0012  * Copyright (c) 2015, Hesham Almatary
0013  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038   #include "config.h"
0039 #endif
0040
0041 #include <rtems/asm.h>
0042
0043 .text
0044 .align 4
0045
0046 PUBLIC(_CPU_Context_switch)
0047 PUBLIC(_CPU_Context_restore)
0048 PUBLIC(_CPU_Context_restore_fp)
0049 PUBLIC(_CPU_Context_save_fp)
0050
0051 SYM(_CPU_Context_switch):
0052     swi     r1,  r5, 0
0053     swi     r13, r5, 4
0054     swi     r14, r5, 8
0055     swi     r15, r5, 12
0056     swi     r16, r5, 16
0057     swi     r17, r5, 20
0058     swi     r18, r5, 24
0059     swi     r19, r5, 28
0060     swi     r20, r5, 32
0061     swi     r21, r5, 36
0062     swi     r22, r5, 40
0063     swi     r23, r5, 44
0064     swi     r24, r5, 48
0065     swi     r25, r5, 52
0066     swi     r26, r5, 56
0067     swi     r27, r5, 60
0068     swi     r28, r5, 64
0069     swi     r29, r5, 68
0070     swi     r30, r5, 72
0071     swi     r31, r5, 76
0072
0073     mfs     r21, rmsr
0074     swi     r21, r5, 80
0075
0076
0077 SYM(restore):
0078     lwi     r1,  r6, 0
0079     lwi     r13, r6, 4
0080     lwi     r14, r6, 8
0081     lwi     r15, r6, 12
0082     lwi     r16, r6, 16
0083     lwi     r17, r6, 20
0084     lwi     r18, r6, 24
0085     lwi     r19, r6, 28
0086     lwi     r20, r6, 32
0087     lwi     r21, r6, 36
0088     lwi     r22, r6, 40
0089     lwi     r23, r6, 44
0090     lwi     r24, r6, 48
0091     lwi     r25, r6, 52
0092     lwi     r26, r6, 56
0093     lwi     r27, r6, 60
0094     lwi     r28, r6, 64
0095     lwi     r29, r6, 68
0096     lwi     r30, r6, 72
0097
0098     lwi     r31, r6, 80
0099     mts     rmsr, r31
0100
0101     lwi     r31, r6, 76
0102
0103     rtsd    r15, 8
0104
0105 SYM(_CPU_Context_restore):
0106     add   r6, r5, r0
0107     brai  restore