cpu/microblaze/cpu_asm.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUMicroBlaze
0007  *
0008  * @brief MicroBlaze interrupt handler implementation
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <rtems/asm.h>
0037 #include <rtems/score/percpu.h>
0038
0039     .text
0040     .globl _ISR_Handler
0041     .align 2
0042
0043 _ISR_Handler:
0044     /* Disable dispatching */
0045     lwi r3, r0, _Per_CPU_Information + 16
0046     addik r3, r3, 1
0047     swi r3, r0, _Per_CPU_Information + 16
0048
0049     /* Is SP < INTERRUPT_STACK_LOW? */
0050     lwi r4, r0, _Per_CPU_Information
0051     rsubk r3, r4, r1
0052     blei r3, switch_to_interrupt_stack
0053
0054     /* Is SP > INTERRUPT_STACK_HIGH? */
0055     lwi r4, r0, _Per_CPU_Information + 4
0056     rsubk r3, r4, r1
0057     bgei r3, switch_to_interrupt_stack
0058
0059     bri on_interrupt_stack
0060
0061 switch_to_interrupt_stack:
0062     add r4, r0, r1
0063     lwi r1, r0, _Per_CPU_Information + 4
0064     addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
0065     swi r4, r1, 0
0066
0067 on_interrupt_stack:
0068     /* Add 1 to ISR_NEST_LEVEL */
0069     lwi r3, r0, _Per_CPU_Information + 8
0070     addik r3, r3, 1
0071     swi r3, r0, _Per_CPU_Information + 8
0072
0073     bralid r15, bsp_interrupt_dispatch
0074     nop
0075
0076     /* Subtract 1 from ISR_NEST_LEVEL */
0077     lwi r3, r0, _Per_CPU_Information + 8
0078     addik r3, r3, -1
0079     swi r3, r0, _Per_CPU_Information + 8
0080
0081     /* Is ISR_NEST_LEVEL > 0? */
0082     bgti r3, after_stack_switch
0083
0084     /* Switch back to interrupted thread stack */
0085     lwi r1, r1, 0
0086
0087 after_stack_switch:
0088     /* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */
0089     lwi r3, r0, _Per_CPU_Information + 16
0090     addik r3, r3, -1
0091     swi r3, r0, _Per_CPU_Information + 16
0092
0093     /* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */
0094     bnei r3, quick_exit
0095
0096     /* Is DISPATCH_NEEDED == 0? */
0097     lwi r3, r0, _Per_CPU_Information + 20
0098     beqi r3, quick_exit
0099
0100     /* Return to interrupted thread and make it do a dispatch */
0101     bralid r15, _Thread_Dispatch
0102     nop
0103     /* Fall through to quick exit */
0104
0105 quick_exit:
0106     /* Simple return from nested interrupt */
0107     /* Restore registers */
0108     lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
0109     mts  rmsr, r3
0110     lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
0111     lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
0112     lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
0113     lwi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
0114     lwi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
0115     lwi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
0116     lwi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
0117     lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
0118     lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
0119     lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
0120     lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
0121     lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
0122     lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
0123
0124     /* Remove stack frame */
0125     addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
0126
0127     rtid r14, 0
0128     nop