cpu/microblaze/cpu.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUMicroBlaze
0007  *
0008  * @brief MicroBlaze architecture support implementation
0009  */
0010
0011 /*
0012  * Copyright (c) 2015, Hesham Almatary
0013  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <inttypes.h>
0042
0043 #include <rtems/bspIo.h>
0044 #include <rtems/fatal.h>
0045 #include <rtems/score/isr.h>
0046 #include <rtems/score/tls.h>
0047 #include <rtems/score/wkspace.h>
0048
0049 void _CPU_Initialize( void )
0050 {
0051 }
0052
0053 void _CPU_Context_Initialize(
0054   Context_Control *context,
0055   void *stack_area_begin,
0056   size_t stack_area_size,
0057   uint32_t new_level,
0058   void (*entry_point)( void ),
0059   bool is_fp,
0060   void *tls_area
0061 )
0062 {
0063   uint32_t stack = (uint32_t) stack_area_begin;
0064   uint32_t stack_high = stack + stack_area_size;
0065
0066   memset( context, 0, sizeof(*context) ) ;
0067
0068   context->r1 = stack_high - 64;
0069   context->r15 = (uint32_t) entry_point;
0070
0071   uint32_t msr;
0072   _CPU_MSR_GET( msr );
0073   context->rmsr = msr;
0074
0075   if ( tls_area != NULL ) {
0076     context->thread_pointer = _TLS_Initialize_area( tls_area );
0077   }
0078 }
0079
0080 void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx )
0081 {
0082   printk(
0083     "\n"
0084     "R0   = 0x%08" PRIx32  " R17  = %p\n"
0085     "R1   = 0x%08" PRIx32  " R18  = 0x%08" PRIx32 "\n"
0086     "R2   = 0x%08" PRIx32  " R19  = 0x%08" PRIx32 "\n"
0087     "R3   = 0x%08" PRIx32  " R20  = 0x%08" PRIx32 "\n"
0088     "R4   = 0x%08" PRIx32  " R21  = 0x%08" PRIx32 "\n"
0089     "R5   = 0x%08" PRIx32  " R22  = 0x%08" PRIx32 "\n"
0090     "R6   = 0x%08" PRIx32  " R23  = 0x%08" PRIx32 "\n"
0091     "R7   = 0x%08" PRIx32  " R24  = 0x%08" PRIx32 "\n"
0092     "R8   = 0x%08" PRIx32  " R25  = 0x%08" PRIx32 "\n"
0093     "R9   = 0x%08" PRIx32  " R26  = 0x%08" PRIx32 "\n"
0094     "R10  = 0x%08" PRIx32  " R27  = 0x%08" PRIx32 "\n"
0095     "R11  = 0x%08" PRIx32  " R28  = 0x%08" PRIx32 "\n"
0096     "R12  = 0x%08" PRIx32  " R29  = 0x%08" PRIx32 "\n"
0097     "R13  = 0x%08" PRIx32  " R30  = 0x%08" PRIx32 "\n"
0098     "R14  = %p"            " R31  = 0x%08" PRIx32 "\n"
0099     "R15  = %p"            " ESR  = 0x%08" PRIx32 "\n"
0100     "R16  = %p"            " EAR  = %p\n",
0101     0,  ctx->r17,
0102     ctx->r1,  ctx->r18,
0103     ctx->r2,  ctx->r19,
0104     ctx->r3,  ctx->r20,
0105     ctx->r4,  ctx->r21,
0106     ctx->r5,  ctx->r22,
0107     ctx->r6,  ctx->r23,
0108     ctx->r7,  ctx->r24,
0109     ctx->r8,  ctx->r25,
0110     ctx->r9,  ctx->r26,
0111     ctx->r10, ctx->r27,
0112     ctx->r11, ctx->r28,
0113     ctx->r12, ctx->r29,
0114     ctx->r13, ctx->r30,
0115     ctx->r14, ctx->r31,
0116     ctx->r15, ctx->esr,
0117     ctx->r16, ctx->ear
0118   );
0119
0120   printk(
0121     "MSR  = 0x%08" PRIx32 " %s%s%s%s%s%s%s%s%s%s%s%s\n",
0122     ctx->msr,
0123     ( ctx->msr & MICROBLAZE_MSR_VM ) ? "VM " : "",
0124     ( ctx->msr & MICROBLAZE_MSR_UM ) ? "UM " : "",
0125     ( ctx->msr & MICROBLAZE_MSR_PVR ) ? "PVR " : "",
0126     ( ctx->msr & MICROBLAZE_MSR_EIP ) ? "EiP " : "",
0127     ( ctx->msr & MICROBLAZE_MSR_EE ) ? "EE " : "",
0128     ( ctx->msr & MICROBLAZE_MSR_DCE ) ? "DCE " : "",
0129     ( ctx->msr & MICROBLAZE_MSR_DZO ) ? "DZO " : "",
0130     ( ctx->msr & MICROBLAZE_MSR_ICE ) ? "ICE " : "",
0131     ( ctx->msr & MICROBLAZE_MSR_FSL ) ? "FSL " : "",
0132     ( ctx->msr & MICROBLAZE_MSR_BIP ) ? "BiP " : "",
0133     ( ctx->msr & MICROBLAZE_MSR_C ) ? "C " : "",
0134     ( ctx->msr & MICROBLAZE_MSR_IE ) ? "IE " : ""
0135   );
0136 }
0137
0138 void _CPU_ISR_Set_level( uint32_t level )
0139 {
0140   uint32_t microblaze_switch_reg;
0141
0142   _CPU_MSR_GET( microblaze_switch_reg );
0143
0144   if ( level == 0 ) {
0145     microblaze_switch_reg |= MICROBLAZE_MSR_IE;
0146   } else {
0147     microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE);
0148   }
0149
0150   _CPU_MSR_SET( microblaze_switch_reg );
0151 }
0152
0153 uint32_t _CPU_ISR_Get_level( void )
0154 {
0155   uint32_t level;
0156
0157   _CPU_MSR_GET( level );
0158
0159   /* This is unique. The MSR register contains an interrupt enable flag where
0160    * most other architectures have an interrupt disable flag. */
0161   return ( level & MICROBLAZE_MSR_IE ) == 0;
0162 }
0163
0164 void _CPU_ISR_install_vector(
0165   uint32_t         vector,
0166   CPU_ISR_handler  new_handler,
0167   CPU_ISR_handler *old_handler
0168 )
0169 {
0170   *old_handler = _ISR_Vector_table[ vector ];
0171   _ISR_Vector_table[ vector ] = new_handler;
0172 }
0173
0174 void *_CPU_Thread_Idle_body( uintptr_t ignored )
0175 {
0176   while ( true ) {
0177   }
0178 }
0179
0180 MicroBlaze_Exception_handler installed_exception_handler = NULL;
0181
0182 void _MicroBlaze_Exception_install_handler(
0183   MicroBlaze_Exception_handler  new_handler,
0184   MicroBlaze_Exception_handler *old_handler
0185 )
0186 {
0187   if ( old_handler != NULL ) {
0188     *old_handler = installed_exception_handler;
0189   }
0190
0191   installed_exception_handler = new_handler;
0192 }
0193
0194 void _MicroBlaze_Exception_handle( CPU_Exception_frame *ef )
0195 {
0196   /* EiP is not set for user exceptions which are unused and not hooked */
0197   if (
0198     ( ef->msr & MICROBLAZE_MSR_EIP ) != 0
0199     && installed_exception_handler != NULL
0200   ) {
0201     installed_exception_handler( ef );
0202   }
0203
0204   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
0205 }
0206
0207 MicroBlaze_Exception_handler installed_debug_handler = NULL;
0208
0209 void _MicroBlaze_Debug_install_handler(
0210   MicroBlaze_Exception_handler  new_handler,
0211   MicroBlaze_Exception_handler *old_handler
0212 )
0213 {
0214   if ( old_handler != NULL ) {
0215     *old_handler = installed_debug_handler;
0216   }
0217
0218   installed_debug_handler = new_handler;
0219 }
0220
0221 void _MicroBlaze_Debug_handle( CPU_Exception_frame *ef )
0222 {
0223   /* BiP is not set for software debug events, set it here */
0224   ef->msr |= MICROBLAZE_MSR_BIP;
0225
0226   if ( installed_debug_handler != NULL ) {
0227     installed_debug_handler( ef );
0228   }
0229
0230   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
0231 }