cpu/lm32/cpu.c

0001 /**
0002  *  @file
0003  *
0004  *  @brief LM32 CPU Dependent Source
0005  */
0006
0007 /*
0008  *  COPYRIGHT (c) 1989-1999.
0009  *  On-Line Applications Research Corporation (OAR).
0010  *
0011  *  The license and distribution terms for this file may be
0012  *  found in the file LICENSE in this distribution or at
0013  *  http://www.rtems.org/license/LICENSE.
0014  *
0015  *  Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
0016  *  Micro-Research Finland Oy
0017  */
0018
0019 #ifdef HAVE_CONFIG_H
0020 #include "config.h"
0021 #endif
0022
0023 #include <rtems/score/cpuimpl.h>
0024 #include <rtems/score/isr.h>
0025
0026 /*  _CPU_Initialize
0027  *
0028  *  This routine performs processor dependent initialization.
0029  *
0030  *  INPUT PARAMETERS: NONE
0031  *
0032  *  LM32 Specific Information:
0033  *
0034  *  XXX document implementation including references if appropriate
0035  */
0036
0037 void _CPU_Initialize(void)
0038 {
0039   /*
0040    *  If there is not an easy way to initialize the FP context
0041    *  during Context_Initialize, then it is usually easier to
0042    *  save an "uninitialized" FP context here and copy it to
0043    *  the task's during Context_Initialize.
0044    */
0045
0046   /* FP context initialization support goes here */
0047 }
0048
0049 uint32_t   _CPU_ISR_Get_level( void )
0050 {
0051   /*
0052    *  This routine returns the current interrupt level.
0053    */
0054
0055   return 0;
0056 }
0057
0058 void _CPU_ISR_install_vector(
0059   uint32_t         vector,
0060   CPU_ISR_handler  new_handler,
0061   CPU_ISR_handler *old_handler
0062 )
0063 {
0064    *old_handler = _ISR_Vector_table[ vector ];
0065
0066    /*
0067     *  We put the actual user ISR address in '_ISR_vector_table'.  This will
0068     *  be used by the _ISR_Handler so the user gets control.
0069     */
0070
0071     _ISR_Vector_table[ vector ] = new_handler;
0072 }
0073
0074 /*
0075  *  _CPU_Thread_Idle_body
0076  *
0077  *  NOTES:
0078  *
0079  *  1. This is the same as the regular CPU independent algorithm.
0080  *
0081  *  2. If you implement this using a "halt", "idle", or "shutdown"
0082  *     instruction, then don't forget to put it in an infinite loop.
0083  *
0084  *  3. Be warned. Some processors with onboard DMA have been known
0085  *     to stop the DMA if the CPU were put in IDLE mode.  This might
0086  *     also be a problem with other on-chip peripherals.  So use this
0087  *     hook with caution.
0088  *
0089  *  LM32 Specific Information:
0090  *
0091  *  XXX document implementation including references if appropriate
0092  */
0093
0094 void *_CPU_Thread_Idle_body( uintptr_t ignored )
0095 {
0096   for( ; ; ) {
0097     /* The LM32 softcore itself hasn't any HLT instruction. But the
0098      * LM32 qemu target interprets this nop instruction as HLT.
0099      */
0100     __asm__ volatile("and r0, r0, r0");
0101  }
0102 }