cpu/bfin/cpu.c

0001 /**
0002  * @file
0003  *
0004  * @brief Blackfin CPU Dependent Source
0005  */
0006
0007 /*
0008  *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
0009  *             written by Alain Schaefer <alain.schaefer@easc.ch>
0010  *                    and Antonio Giovanini <antonio@atos.com.br>
0011  *
0012  *  The license and distribution terms for this file may be
0013  *  found in the file LICENSE in this distribution or at
0014  *  http://www.rtems.org/license/LICENSE.
0015  */
0016
0017 #ifdef HAVE_CONFIG_H
0018 #include "config.h"
0019 #endif
0020
0021 #include <rtems/score/cpuimpl.h>
0022 #include <rtems/score/isr.h>
0023 #include <rtems/score/bfin.h>
0024 #include <rtems/bfin/bfin.h>
0025
0026 /*  _CPU_Initialize
0027  *
0028  *  This routine performs processor dependent initialization.
0029  *
0030  *  INPUT PARAMETERS: NONE
0031  *
0032  *  NO_CPU Specific Information:
0033  *
0034  *  XXX document implementation including references if appropriate
0035  */
0036
0037
0038 extern void _ISR15_Handler(void);
0039 extern void _CPU_Emulation_handler(void);
0040 extern void _CPU_Reset_handler(void);
0041 extern void _CPU_NMI_handler(void);
0042 extern void _CPU_Exception_handler(void);
0043 extern void _CPU_Unhandled_Interrupt_handler(void);
0044
0045 void _CPU_Initialize(void)
0046 {
0047   /*
0048    *  If there is not an easy way to initialize the FP context
0049    *  during Context_Initialize, then it is usually easier to
0050    *  save an "uninitialized" FP context here and copy it to
0051    *  the task's during Context_Initialize.
0052    */
0053
0054   /* FP context initialization support goes here */
0055
0056
0057
0058   CPU_ISR_raw_handler ignored;
0059
0060 #if 0
0061   /* occassionally useful debug stuff */
0062   int i;
0063   _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
0064   _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
0065   _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
0066   _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
0067   for (i = 5; i < 15; i++)
0068     _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
0069 #endif
0070
0071   /* install handler that will be used to call _Thread_Dispatch */
0072   _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
0073   /* enable self nesting */
0074   __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
0075 }
0076
0077 /*
0078  *  _CPU_ISR_Get_level
0079  *
0080  *  NO_CPU Specific Information:
0081  *
0082  *  XXX document implementation including references if appropriate
0083  */
0084
0085 uint32_t   _CPU_ISR_Get_level( void )
0086 {
0087   /*
0088    *  This routine returns the current interrupt level.
0089    */
0090
0091     register uint32_t   _tmpimask;
0092
0093     /*read from the IMASK registers*/
0094
0095     _tmpimask = *((uint32_t*)IMASK);
0096
0097     return (_tmpimask & 0xffe0) ? 0 : 1;
0098 }
0099
0100 void _CPU_ISR_install_raw_handler(
0101   uint32_t             vector,
0102   CPU_ISR_raw_handler  new_handler,
0103   CPU_ISR_raw_handler *old_handler
0104 )
0105 {
0106    CPU_ISR_raw_handler *interrupt_table;
0107
0108   /*
0109    *  This is where we install the interrupt handler into the "raw" interrupt
0110    *  table used by the CPU to dispatch interrupt handlers.
0111    */
0112
0113    /* base of vector table on blackfin architecture */
0114    interrupt_table = (void*)0xFFE02000;
0115
0116    *old_handler = interrupt_table[ vector ];
0117    interrupt_table[ vector ] = new_handler;
0118
0119 }
0120
0121 void _CPU_ISR_install_vector(
0122   uint32_t         vector,
0123   CPU_ISR_handler  new_handler,
0124   CPU_ISR_handler *old_handler
0125 )
0126 {
0127    CPU_ISR_raw_handler ignored;
0128
0129    *old_handler = _ISR_Vector_table[ vector ];
0130
0131    /*
0132     *  We put the actual user ISR address in '_ISR_vector_table'.  This will
0133     *  be used by the _ISR_Handler so the user gets control.
0134     */
0135
0136     _ISR_Vector_table[ vector ] = new_handler;
0137
0138     _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
0139 }
0140
0141 void *_CPU_Thread_Idle_body(uintptr_t ignored)
0142 {
0143   while (1) {
0144     __asm__ __volatile__("ssync; idle; ssync");
0145   }
0146 }
0147
0148 /*
0149  * Copied from the arm port.
0150  */
0151 void _CPU_Context_Initialize(
0152   Context_Control  *the_context,
0153   uint32_t         *stack_base,
0154   uint32_t          size,
0155   uint32_t          new_level,
0156   void             *entry_point,
0157   bool              is_fp,
0158   void             *tls_area
0159 )
0160 {
0161     uint32_t     stack_high;  /* highest "stack aligned" address */
0162     stack_high = ((uint32_t)(stack_base) + size);
0163
0164     /* blackfin abi requires caller to reserve 12 bytes on stack */
0165     the_context->register_sp = stack_high - 12;
0166     the_context->register_rets = (uint32_t) entry_point;
0167     the_context->imask = new_level ? 0 : 0xffff;
0168 }