include/rtems/asm.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUARMASM
0007  *
0008  * @brief This header file provides interfaces to address problems caused by
0009  *   incompatible flavor of assemblers and toolsets.
0010  *
0011  * This include file attempts to address the problems
0012  * caused by incompatible flavors of assemblers and
0013  * toolsets.  It primarily addresses variations in the
0014  * use of leading underscores on symbols and the requirement
0015  * that register names be preceded by a %.
0016  *
0017  *
0018  * NOTE: The spacing in the use of these macros
0019  *       is critical to them working as advertised.
0020  */
0021
0022 /*
0023  *  COPYRIGHT:
0024  *
0025  *  This file is based on similar code found in newlib available
0026  *  from ftp.cygnus.com.  The file which was used had no copyright
0027  *  notice.  This file is freely distributable as long as the source
0028  *  of the file is noted.  This file is:
0029  *
0030  *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
0031  *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
0032  *
0033  * Redistribution and use in source and binary forms, with or without
0034  * modification, are permitted provided that the following conditions
0035  * are met:
0036  * 1. Redistributions of source code must retain the above copyright
0037  *    notice, this list of conditions and the following disclaimer.
0038  * 2. Redistributions in binary form must reproduce the above copyright
0039  *    notice, this list of conditions and the following disclaimer in the
0040  *    documentation and/or other materials provided with the distribution.
0041  *
0042  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0043  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0044  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0045  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0046  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0047  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0048  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0049  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0050  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0051  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0052  * POSSIBILITY OF SUCH DAMAGE.
0053  *
0054  */
0055
0056 #ifndef _RTEMS_ASM_H
0057 #define _RTEMS_ASM_H
0058
0059 /*
0060  *  Indicate we are in an assembly file and get the basic CPU definitions.
0061  */
0062
0063 #ifndef ASM
0064 #define ASM
0065 #endif
0066 #include <rtems/score/percpu.h>
0067
0068 /**
0069  * @defgroup RTEMSScoreCPUARMASM ARM Assembler Support
0070  *
0071  * @ingroup RTEMSScoreCPUARM
0072  *
0073  * @brief ARM Assembler Support
0074  */
0075 /**@{**/
0076
0077 /*
0078  *  Recent versions of GNU cpp define variables which indicate the
0079  *  need for underscores and percents.  If not using GNU cpp or
0080  *  the version does not support this, then you will obviously
0081  *  have to define these as appropriate.
0082  */
0083
0084 #ifndef __USER_LABEL_PREFIX__
0085 #define __USER_LABEL_PREFIX__ _
0086 #endif
0087
0088 #ifndef __REGISTER_PREFIX__
0089 #define __REGISTER_PREFIX__
0090 #endif
0091
0092 /* Use the right prefix for global labels.  */
0093
0094 #define SYM(x) RTEMS_XCONCAT(__USER_LABEL_PREFIX__, x)
0095
0096 /* Use the right prefix for registers.  */
0097
0098 #define REG(x) RTEMS_XCONCAT(__REGISTER_PREFIX__, x)
0099
0100 /*
0101  *  define macros for all of the registers on this CPU
0102  *
0103  *  EXAMPLE:     #define d0 REG (d0)
0104  */
0105
0106 #define r0  REG(r0)
0107 #define r1  REG(r1)
0108 #define r2  REG(r2)
0109 #define r3  REG(r3)
0110 #define r4  REG(r4)
0111 #define r5  REG(r5)
0112 #define r6  REG(r6)
0113 #define r7  REG(r7)
0114 #define r8  REG(r8)
0115 #define r9  REG(r9)
0116 #define r10 REG(r10)
0117 #define r11 REG(r11)
0118 #define r12 REG(r12)
0119 #define r13 REG(r13)
0120 #define r14 REG(r14)
0121 #define r15 REG(r15)
0122
0123 #define CPSR REG(CPSR)
0124
0125 #define SPSR REG(SPSR)
0126
0127 #define NUM_IRQ_VECTOR          6       // IRQ number
0128 #define NUM_FIQ_VECTOR          7       // IRQ number
0129                                         //                                      //
0130 #define CPSR_IRQ_DISABLE        0x80    // FIQ disabled when =1
0131 #define CPSR_FIQ_DISABLE        0x40    // FIQ disabled when =1
0132 #define CPSR_THUMB_ENABLE       0x20    // Thumb mode when =1
0133 #define CPSR_FIQ_MODE           0x11
0134 #define CPSR_IRQ_MODE           0x12
0135 #define CPSR_SUPERVISOR_MODE    0x13
0136 #define CPSR_UNDEF_MODE         0x1B
0137
0138 #define CPSR_MODE_BITS          0x1F
0139
0140 /*
0141  *  Define macros to handle section beginning and ends.
0142  */
0143
0144
0145 #define BEGIN_CODE_DCL .text
0146 #define END_CODE_DCL
0147 #define BEGIN_DATA_DCL .data
0148 #define END_DATA_DCL
0149 #define BEGIN_CODE .text
0150 #define END_CODE
0151 #define BEGIN_DATA
0152 #define END_DATA
0153 #define BEGIN_BSS
0154 #define END_BSS
0155 #define END
0156
0157 /*
0158  *  Following must be tailor for a particular flavor of the C compiler.
0159  *  They may need to put underscores in front of the symbols.
0160  */
0161
0162 #define PUBLIC(sym) .globl SYM (sym)
0163 #define EXTERN(sym) .globl SYM (sym)
0164
0165 #define FUNCTION_THUMB_ENTRY(name) \
0166   .thumb; \
0167   .thumb_func; \
0168   .align 2; \
0169   .globl name; \
0170   .type name, %function; \
0171   name:
0172
0173 #define FUNCTION_ENTRY(name) \
0174   .align 2; \
0175   .globl name; \
0176   .type name, %function; \
0177   name:
0178
0179 #define FUNCTION_END(name) \
0180   .size name, . - name
0181
0182 #if defined(ARM_MULTILIB_ARCH_V7M)
0183   #define DEFINE_FUNCTION_ARM(name) \
0184     .thumb_func ; .globl name ; name:
0185 #elif defined(__thumb__)
0186   #define DEFINE_FUNCTION_ARM(name) \
0187     .thumb_func ; .globl name ; name: ; bx pc ; \
0188     .arm ; .globl name ## _arm ; name ## _arm:
0189 #else
0190   #define DEFINE_FUNCTION_ARM(name) \
0191     .globl name ; name: ; .globl name ## _arm ; name ## _arm:
0192 #endif
0193
0194 .macro SWITCH_FROM_THUMB_TO_ARM
0195 #ifdef __thumb__
0196 .align 2
0197     bx  pc
0198 .arm
0199 #endif /* __thumb__ */
0200 .endm
0201
0202 .macro SWITCH_FROM_ARM_TO_THUMB REG
0203 #ifdef __thumb__
0204     add \REG, pc, #1
0205     bx  \REG
0206 .thumb
0207 #endif /* __thumb__ */
0208 .endm
0209
0210 .macro SWITCH_FROM_THUMB_2_TO_ARM
0211 #ifdef __thumb2__
0212 .align 2
0213     bx  pc
0214 .arm
0215 #endif /* __thumb__ */
0216 .endm
0217
0218 .macro SWITCH_FROM_ARM_TO_THUMB_2 REG
0219 #ifdef __thumb2__
0220     add \REG, pc, #1
0221     bx  \REG
0222 .thumb
0223 #endif /* __thumb__ */
0224 .endm
0225
0226 .macro BLX_TO_THUMB_1 TARGET
0227 #if defined(__thumb__) && !defined(__thumb2__)
0228     add lr, pc, #1
0229     bx  lr
0230 .thumb
0231     bl  \TARGET
0232 .align 2
0233     bx  pc
0234 .arm
0235 #else
0236     bl  \TARGET
0237 #endif
0238 .endm
0239
0240 .macro GET_SELF_CPU_CONTROL REG
0241 #ifdef RTEMS_SMP
0242     /* Use PL1 only Thread ID Register (TPIDRPRW) */
0243     mrc p15, 0, \REG, c13, c0, 4
0244 #else
0245     ldr \REG, =_Per_CPU_Information
0246 #endif
0247 .endm
0248
0249 /** @} */
0250
0251 #endif /* _RTEMS_ASM_H */