cpu/arm/armv7m-isr-dispatch.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUARM
0007  *
0008  * @brief This source file contains the implementation of
0009  *   _ARMV7M_Thread_dispatch().
0010  */
0011
0012 /*
0013  * Copyright (c) 2011, 2017 Sebastian Huber.  All rights reserved.
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/armv7m.h>
0042 #include <rtems/score/percpu.h>
0043
0044 #ifdef ARM_MULTILIB_ARCH_V7M
0045
0046 static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
0047 {
0048   __asm__ volatile (
0049     "bl _Thread_Dispatch\n"
0050     /* FIXME: SVC, binutils bug */
0051     ".short 0xdf00\n"
0052     "nop\n"
0053   );
0054 }
0055
0056 static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
0057 {
0058 #ifdef ARM_MULTILIB_VFP
0059   __asm__ volatile (
0060     "vmov.f32 s0, s0\n"
0061     : : : "memory"
0062   );
0063 #endif
0064 }
0065
0066 void _ARMV7M_Pendable_service_call( void )
0067 {
0068   Per_CPU_Control *cpu_self = _Per_CPU_Get();
0069
0070   /*
0071    * We must check here if a thread dispatch is allowed.  Right after a
0072    * "msr basepri_max, %[basepri]" instruction an interrupt service may still
0073    * take place.  However, pendable service calls that are activated during
0074    * this interrupt service may be delayed until interrupts are enable again.
0075    */
0076   if (
0077     ( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0
0078   ) {
0079     volatile ARMV7M_SCB *scb = _ARMV7M_SCB;
0080     ARMV7M_Exception_frame *ef;
0081
0082     cpu_self->isr_nest_level = 1;
0083
0084     scb->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
0085     _ARMV7M_Trigger_lazy_floating_point_context_save();
0086 #ifdef ARM_MULTILIB_VFP
0087     /*
0088      * Set FPCCR[LSPACT] to mark the lazy state preservation as active.  This
0089      * prevents that a floating-point context is restored from the
0090      * uninitialized exception frame below in the return to
0091      * _ARMV7M_Thread_dispatch().
0092      */
0093     scb->fpccr |= 0x1;
0094 #endif
0095
0096     ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
0097     --ef;
0098     _ARMV7M_Set_PSP( (uint32_t) ef );
0099
0100     /*
0101      * According to "ARMv7-M Architecture Reference Manual" section B1.5.6
0102      * "Exception entry behavior" the return address is half-word aligned.
0103      */
0104     ef->register_pc = (void *)
0105       ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
0106
0107     ef->register_xpsr = 0x01000000U;
0108   }
0109 }
0110
0111 void _ARMV7M_Supervisor_call( void )
0112 {
0113   Per_CPU_Control *cpu_self = _Per_CPU_Get();
0114   ARMV7M_Exception_frame *ef;
0115
0116   _ARMV7M_Trigger_lazy_floating_point_context_save();
0117
0118   ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
0119   ++ef;
0120   _ARMV7M_Set_PSP( (uint32_t) ef );
0121
0122   cpu_self->isr_nest_level = 0;
0123
0124   if ( cpu_self->dispatch_necessary ) {
0125     _ARMV7M_Pendable_service_call();
0126   }
0127 }
0128
0129 #endif /* ARM_MULTILIB_ARCH_V7M */