cpu/arm/armv7m-exception-default.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUARM
0007  *
0008  * @brief This source file contains the implementation of
0009  *   _ARMV7M_Exception_default().
0010  */
0011
0012 /*
0013  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/armv7m.h>
0042
0043 #ifdef ARM_MULTILIB_ARCH_V7M
0044
0045 void __attribute__((naked)) _ARMV7M_Exception_default( void )
0046 {
0047     /* On exception entry, ARMv7M saves context state onto a stack pointed to
0048      * by either MSP or PSP. The value stored in LR indicates whether we were
0049      * in Thread or Handler mode, whether we were using the FPU (if any),
0050      * and which stack pointer we were using.
0051      * In particular, bit 2 of LR will be 0 if we were using MSP.
0052      *
0053      * For a more detailed explanation, see the Exception Entry Behavior
0054      * section of the ARMv7M Architecture Reference Manual.
0055      */
0056
0057     /* As we're in Handler mode here, we'll always operate on MSP.
0058      * However, we need to store the right SP in our CPU_Exception_frame.
0059      */
0060   __asm__ volatile (
0061     "sub sp, %[cpufsz]\n"   /* Allocate space for a CPU_Exception_frame. */
0062     "stm sp, {r0-r12}\n"
0063     "tst lr, #4\n"          /* Check if bit 2 of LR is zero. If so, PSR.Z = 1 */
0064     "itte eq\n"             /* IF bit 2 of LR is zero... (PSR.Z == 1) */
0065     "mrseq r3, msp\n"       /* THEN we were using MSP */
0066     "addeq r3, %[cpufsz]\n" /* THEN, set r3 = old MSP value */
0067     "mrsne r3, psp\n"       /* ELSE it is not zero; we were using PSP */
0068     "add r2, r3, %[v7mlroff]\n"
0069     "add r1, sp, %[cpuspoff]\n"
0070     "ldm r2, {r4-r6}\n"     /* Grab LR, PC and xPSR from the stack */
0071     "tst lr, #16\n"         /* Check if we have an FP state on the frame */
0072     "ite eq\n"
0073     "addeq r3, #104\n"      /* Back to previous SP with FP state */
0074     "addne r3, #32\n"       /* Back to previous SP without FP state */
0075     "tst r6, #512\n"        /* Check xPSR if the SP was aligned */
0076     "it ne\n"
0077     "addne r3, #4\n"        /* Undo alignment */
0078     "stm r1, {r3-r6}\n"     /* Store to CPU_Exception_frame */
0079     "mrs r1, ipsr\n"
0080     "str r1, [sp, %[cpuvecoff]]\n"
0081
0082     /* Argument for high level handler */
0083     "mov r0, sp\n"
0084
0085     /* Clear VFP context pointer */
0086     "add r3, sp, %[cpuvfpoff]\n"
0087     "mov r1, #0\n"
0088     "str r1, [r3]\n"
0089
0090 #ifdef ARM_MULTILIB_VFP
0091     /* Ensure that the FPU is enabled */
0092     "ldr r4, =%[cpacr]\n"
0093     "tst r4, #(0xf << 20)\n"
0094     "bne 1f\n"
0095
0096     /* Save VFP context */
0097     "sub sp, %[vfpsz]\n"
0098     "add r4, sp, #4\n"
0099     "bic r4, r4, #7\n"
0100     "str r4, [r3]\n"
0101     "vmrs r2, FPSCR\n"
0102     "stmia r4!, {r1-r2}\n"
0103     "vstmia r4!, {d0-d15}\n"
0104     "mov r1, #0\n"
0105     "mov r2, #0\n"
0106     "adds r3, r4, #128\n"
0107     "2:\n"
0108     "stmia r4!, {r1-r2}\n"
0109     "cmp r4, r3\n"
0110     "bne 2b\n"
0111     "1:\n"
0112 #endif
0113
0114     "b _ARM_Exception_default\n"
0115     :
0116     : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
0117       [cpuspoff] "i" (offsetof(CPU_Exception_frame, register_sp)),
0118       [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
0119       [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),
0120       [cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET),
0121       [cpacr] "i" (ARMV7M_CPACR),
0122       [vfpsz] "i" (ARM_VFP_CONTEXT_SIZE)
0123   );
0124 }
0125
0126 #endif /* ARM_MULTILIB_ARCH_V7M */