cpu/arm/armv7m-context-restore.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUARM
0007  *
0008  * @brief This source file contains the implementation of
0009  *   _CPU_Context_restore().
0010  */
0011
0012 /*
0013  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifdef HAVE_CONFIG_H
0038 #include "config.h"
0039 #endif
0040
0041 #include <rtems/score/armv7m.h>
0042 #include <rtems/score/percpu.h>
0043
0044 #ifdef ARM_MULTILIB_ARCH_V7M
0045
0046 void __attribute__((naked)) _CPU_Context_restore(
0047   Context_Control *heir
0048 )
0049 {
0050   __asm__ volatile (
0051     "movw r2, #:lower16:_Per_CPU_Information\n"
0052     "movt r2, #:upper16:_Per_CPU_Information\n"
0053     "ldr r3, [r0, %[isrctxoff]]\n"
0054     "ldr sp, [r0, %[spctxoff]]\n"
0055     "ldm r0, {r4-r11, lr}\n"
0056     "str r3, [r2, %[isrpcpuoff]]\n"
0057     "bx lr\n"
0058     :
0059     : [spctxoff] "J" (offsetof(Context_Control, register_sp)),
0060       [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)),
0061       [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level))
0062   );
0063   __builtin_unreachable();
0064 }
0065
0066 #endif /* ARM_MULTILIB_ARCH_V7M */