cpu/arm/armv4-exception-resume.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2024 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #ifdef HAVE_CONFIG_H
0029 #include "config.h"
0030 #endif
0031
0032 #include <rtems/asm.h>
0033
0034 #ifdef ARM_MULTILIB_ARCH_V4
0035
0036 .section ".text"
0037
0038 .arm
0039
0040 FUNCTION_ENTRY(_CPU_Exception_resume)
0041
0042 #ifdef ARM_MULTILIB_VFP
0043     ldr r1, [r0, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET]
0044     cmp r1, #0
0045     beq .Lvfp_restore_done
0046
0047     /* Restore FPEXC, FPSCR, and D0-D31 */
0048     ldmia   r1!, {r2-r3}
0049     vmsr    FPEXC, r2
0050     vmsr    FPSCR, r3
0051     vstmia  r1!, {d0-d15}
0052 #ifdef ARM_MULTILIB_VFP_D32
0053     vstmia  r1!, {d16-d31}
0054 #endif
0055
0056 .Lvfp_restore_done:
0057 #endif /* ARM_MULTILIB_VFP */
0058
0059     /*
0060      * Restore the original stack pointer of the exception mode.  Assume
0061      * that the exception frame was produced by a default exception
0062      * handler.
0063      */
0064     mov sp, r0
0065
0066     ldr r1, [r0, #ARM_EXCEPTION_FRAME_REGISTER_PC_OFFSET]
0067     ldr r2, [r0, #ARM_EXCEPTION_FRAME_REGISTER_CPSR_OFFSET]
0068     mov lr, r1
0069     msr spsr, r2
0070     mrs r3, cpsr
0071     bic r4, r2, #(ARM_PSR_I | ARM_PSR_F)
0072     and r5, r3, #(ARM_PSR_I | ARM_PSR_F)
0073     orr r4, r4, r5
0074
0075     /* We assume that we do not resume to user mode */
0076     msr cpsr, r4
0077
0078     /* Restore potentially banked registers in the mode to resume */
0079     add r1, r0, #ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET
0080     ldm r1, {r8-r13}
0081
0082     msr cpsr, r3
0083     ldm r0, {r0-r7}
0084     movs    pc, lr
0085
0086 FUNCTION_END(_CPU_Exception_resume)
0087
0088 #endif /* ARM_MULTILIB_ARCH_V4 */