cpu/arm/armv4-exception-default.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUARM
0007  *
0008  * @brief This source file contains the default exception handlers.
0009  */
0010
0011 /*
0012  * Copyright (c) 2013, 2024 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifdef HAVE_CONFIG_H
0037 #include "config.h"
0038 #endif
0039
0040 #include <rtems/asm.h>
0041
0042 #ifdef ARM_MULTILIB_ARCH_V4
0043
0044 #define MORE_CONTEXT_SIZE \
0045   (ARM_EXCEPTION_FRAME_SIZE - ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET)
0046
0047 .extern _ARM_Exception_default
0048
0049 .globl _ARMV4_Exception_undef_default
0050 .globl _ARMV4_Exception_swi_default
0051 .globl _ARMV4_Exception_data_abort_default
0052 .globl _ARMV4_Exception_pref_abort_default
0053 .globl _ARMV4_Exception_fiq_default
0054
0055 .section ".text"
0056
0057 .arm
0058
0059 _ARMV4_Exception_undef_default:
0060
0061     /* Save context and load vector */
0062     sub sp, #MORE_CONTEXT_SIZE
0063     stmdb   sp!, {r0-r7}
0064     mov r4, #1
0065     mov r5, #ARM_PSR_I
0066
0067     b   save_more_context
0068
0069 _ARMV4_Exception_swi_default:
0070
0071     /* Save context and load vector */
0072     sub sp, #MORE_CONTEXT_SIZE
0073     stmdb   sp!, {r0-r7}
0074     mov r4, #2
0075     mov r5, #ARM_PSR_I
0076
0077     b   save_more_context
0078
0079 _ARMV4_Exception_pref_abort_default:
0080
0081     /* Save context and load vector */
0082     sub sp, #MORE_CONTEXT_SIZE
0083     stmdb   sp!, {r0-r7}
0084     mov r4, #3
0085     mov r5, #ARM_PSR_I
0086
0087     b   save_more_context
0088
0089 _ARMV4_Exception_data_abort_default:
0090
0091     /* Save context and load vector */
0092     sub sp, #MORE_CONTEXT_SIZE
0093     stmdb   sp!, {r0-r7}
0094     mov r4, #4
0095     mov r5, #ARM_PSR_I
0096
0097     b   save_more_context
0098
0099 _ARMV4_Exception_fiq_default:
0100
0101     /* Save context and load vector */
0102     sub sp, #MORE_CONTEXT_SIZE
0103     stmdb   sp!, {r0-r7}
0104     mov r4, #7
0105     mov r5, #(ARM_PSR_I | ARM_PSR_F)
0106
0107 save_more_context:
0108
0109     /* Save more context, clear VFP context pointer */
0110     mov r2, lr
0111     mrs r3, spsr
0112     mrs r7, cpsr
0113     orr r5, r5, r3
0114     add r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_R8_OFFSET
0115     add sp, #ARM_EXCEPTION_FRAME_SIZE
0116     msr cpsr, r5
0117     stmia   r6!, {r8-r14}
0118     msr cpsr, r7
0119     sub sp, #ARM_EXCEPTION_FRAME_SIZE
0120     mov r5, #0
0121     stm r6, {r2-r5}
0122
0123     /* Argument for high level handler */
0124     mov r0, sp
0125
0126 #ifdef ARM_MULTILIB_VFP
0127     /* Ensure that the FPU is enabled */
0128     vmrs    r1, FPEXC
0129     tst r1, #(1 << 30)
0130     beq 1f
0131
0132     /* Save VFP context */
0133     sub sp, #(ARM_VFP_CONTEXT_SIZE + 8)
0134     add r4, sp, #8
0135     bic r4, r4, #7
0136     str r4, [r0, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET]
0137     vmrs    r2, FPSCR
0138     stmia   r4!, {r1-r2}
0139     vstmia  r4!, {d0-d15}
0140 #ifdef ARM_MULTILIB_VFP_D32
0141     vstmia  r4!, {d16-d31}
0142 #else
0143     mov r1, #0
0144     mov r2, #0
0145     adds    r3, r4, #128
0146 2:
0147     stmia   r4!, {r1-r2}
0148     cmp r4, r3
0149     bne 2b
0150 #endif
0151 1:
0152 #endif /* ARM_MULTILIB_VFP */
0153
0154     /* Call high level handler */
0155     SWITCH_FROM_ARM_TO_THUMB    r1
0156     bl  _ARM_Exception_default
0157
0158 #endif /* ARM_MULTILIB_ARCH_V4 */