include/libcpu/mmu-vmsav8-64.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUAArch64
0007  *
0008  * @brief Definitions used in MMU setup.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBCPU_AARCH64_MMU_VMSAV8_64_H
0038 #define LIBCPU_AARCH64_MMU_VMSAV8_64_H
0039
0040 #ifndef ASM
0041
0042 #ifdef __cplusplus
0043 extern "C" {
0044 #endif /* __cplusplus */
0045
0046 #include <rtems.h>
0047
0048 /* VMSAv8 Long-descriptor fields */
0049 #define MMU_DESC_AF                        ( 1 << 10 )
0050 #define MMU_DESC_SH_INNER                  ( ( 1 << 9 ) | ( 1 << 8 ) )
0051 #define MMU_DESC_WRITE_DISABLE             ( 1 << 7 )
0052 /* PAGE and TABLE flags are the same bit, but only apply on certain levels */
0053 #define MMU_DESC_TYPE_TABLE                ( 1 << 1 )
0054 #define MMU_DESC_TYPE_PAGE                 ( 1 << 1 )
0055 #define MMU_DESC_VALID                     ( 1 << 0 )
0056 #define MMU_DESC_MAIR_ATTR( val )          ( ( val & 0x3 ) << 2 )
0057 #define MMU_DESC_PAGE_TABLE_MASK           0xFFFFFFFFF000LL
0058
0059 /* Page table configuration */
0060 #define MMU_PAGE_BITS           12
0061 #define MMU_PAGE_SIZE           ( 1 << MMU_PAGE_BITS )
0062 #define MMU_BITS_PER_LEVEL      9
0063
0064 #define AARCH64_MMU_FLAGS_BASE \
0065   ( MMU_DESC_VALID | MMU_DESC_SH_INNER | MMU_DESC_AF )
0066
0067 #define AARCH64_MMU_DATA_RO_CACHED \
0068   ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) | MMU_DESC_WRITE_DISABLE )
0069 #define AARCH64_MMU_CODE_CACHED AARCH64_MMU_DATA_RO_CACHED
0070 #define AARCH64_MMU_CODE_RW_CACHED AARCH64_MMU_DATA_RW_CACHED
0071
0072 #define AARCH64_MMU_DATA_RO \
0073   ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) | MMU_DESC_WRITE_DISABLE )
0074 #define AARCH64_MMU_CODE AARCH64_MMU_DATA_RO
0075 #define AARCH64_MMU_CODE_RW AARCH64_MMU_DATA_RW
0076
0077 /* RW implied by not ORing in RO */
0078 #define AARCH64_MMU_DATA_RW_CACHED \
0079   ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) )
0080 #define AARCH64_MMU_DATA_RW \
0081   ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) )
0082 #define AARCH64_MMU_DEVICE ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 0 ) )
0083
0084 rtems_status_code aarch64_mmu_map(
0085   uintptr_t addr,
0086   uint64_t  size,
0087   uint64_t  flags
0088 );
0089
0090 #ifdef __cplusplus
0091 }
0092 #endif /* __cplusplus */
0093
0094 #endif /* ASM */
0095
0096 #endif /* LIBCPU_AARCH64_MMU_VMSAV8_64_H */