cpu/aarch64/aarch64-exception-frame.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreCPUAArch64
0007  *
0008  * @brief This source file contains the implementation of
0009  *   _CPU_Exception_disable_thread_dispatch(),
0010  *   _CPU_Exception_frame_get_signal(), _CPU_Exception_frame_set_resume(), and
0011  *   _CPU_Exception_frame_make_resume_next_instruction().
0012  */
0013
0014 /*
0015  * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
0016  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0017  *
0018  * Redistribution and use in source and binary forms, with or without
0019  * modification, are permitted provided that the following conditions
0020  * are met:
0021  * 1. Redistributions of source code must retain the above copyright
0022  *    notice, this list of conditions and the following disclaimer.
0023  * 2. Redistributions in binary form must reproduce the above copyright
0024  *    notice, this list of conditions and the following disclaimer in the
0025  *    documentation and/or other materials provided with the distribution.
0026  *
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0028  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0029  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0030  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0031  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0032  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0033  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0036  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGE.
0038  */
0039
0040 #ifdef HAVE_CONFIG_H
0041 #include "config.h"
0042 #endif
0043
0044 #include <rtems/score/cpu.h>
0045
0046 #include <rtems/score/aarch64-system-registers.h>
0047 #include <rtems/score/percpu.h>
0048
0049 void _CPU_Exception_disable_thread_dispatch( void )
0050 {
0051   Per_CPU_Control *cpu_self = _Per_CPU_Get();
0052
0053   /* Increment interrupt nest and thread dispatch disable level */
0054   ++cpu_self->thread_dispatch_disable_level;
0055   ++cpu_self->isr_nest_level;
0056 }
0057
0058 void _AArch64_Exception_frame_copy(
0059   CPU_Exception_frame *new_ef,
0060   CPU_Exception_frame *old_ef
0061 )
0062 {
0063   *new_ef = *old_ef;
0064 }
0065
0066 int _CPU_Exception_frame_get_signal( CPU_Exception_frame *ef )
0067 {
0068   uint64_t EC = AARCH64_ESR_EL1_EC_GET( ef->register_syndrome );
0069
0070   switch ( EC ) {
0071     case 0x1:  /* WFI */
0072     case 0x7:  /* SVE/SIMD/FP */
0073     case 0xa:  /* LD64B/ST64B* */
0074     case 0x18: /* MSR/MRS/system instruction */
0075     case 0x19: /* SVE */
0076     case 0x15: /* Supervisor call */
0077     case 0x26: /* SP Alignment */
0078     case 0x31: /* Breakpoint */
0079     case 0x33: /* Step */
0080     case 0x35: /* Watchpoint */
0081     case 0x3c: /* Break Instruction */
0082       return -1;
0083     case 0x2c: /* FPU */
0084       return SIGFPE;
0085     case 0x21: /* Instruction Abort */
0086     case 0x25: /* Data Abort */
0087       return SIGSEGV;
0088     default:
0089       return SIGILL;
0090   }
0091 }
0092
0093 void _CPU_Exception_frame_set_resume( CPU_Exception_frame *ef, void *address )
0094 {
0095   ef->register_pc = address;
0096 }
0097
0098 #define AARCH64_INSTRUCTION_SIZE 4
0099 void  _CPU_Exception_frame_make_resume_next_instruction( CPU_Exception_frame *ef )
0100 {
0101   ef->register_pc += AARCH64_INSTRUCTION_SIZE;
0102 }