rtems/score/smpbarrier.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSScoreSMPBarrier
0007  *
0008  * @brief This header file provides the interfaces of the
0009  *   @ref RTEMSScoreSMPBarrier.
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2024 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef _RTEMS_SCORE_SMPBARRIER_H
0038 #define _RTEMS_SCORE_SMPBARRIER_H
0039
0040 #include <rtems/score/cpuopts.h>
0041 #include <rtems/score/atomic.h>
0042
0043 #ifdef __cplusplus
0044 extern "C" {
0045 #endif /* __cplusplus */
0046
0047 /**
0048  * @defgroup RTEMSScoreSMPBarrier SMP Barriers
0049  *
0050  * @ingroup RTEMSScore
0051  *
0052  * @brief This group contains the SMP barrier implementation.
0053  *
0054  * The SMP barrier provides barrier synchronization for SMP systems at the
0055  * lowest level.
0056  *
0057  * The SMP barrier is implemented as a sense barrier, see also Herlihy and
0058  * Shavit, "The Art of Multiprocessor Programming", 17.3 Sense-Reversing
0059  * Barrier.
0060  *
0061  * @{
0062  */
0063
0064 /**
0065  * @brief SMP barrier control.
0066  */
0067 typedef struct {
0068   Atomic_Uint value;
0069   Atomic_Uint sense;
0070 } SMP_barrier_Control;
0071
0072 /**
0073  * @brief SMP barrier per-thread state.
0074  *
0075  * Each user of the barrier must provide this per-thread state.
0076  */
0077 typedef struct {
0078   unsigned int sense;
0079 } SMP_barrier_State;
0080
0081 /**
0082  * @brief SMP barrier control initializer for static initialization.
0083  */
0084 #define SMP_BARRIER_CONTROL_INITIALIZER \
0085   { ATOMIC_INITIALIZER_UINT( 0U ), ATOMIC_INITIALIZER_UINT( 0U ) }
0086
0087 /**
0088  * @brief SMP barrier per-thread state initializer for static initialization.
0089  */
0090 #define SMP_BARRIER_STATE_INITIALIZER { 0U }
0091
0092 /**
0093  * @brief Initializes a SMP barrier control.
0094  *
0095  * Concurrent initialization leads to unpredictable results.
0096  *
0097  * @param[out] control The SMP barrier control.
0098  */
0099 static inline void _SMP_barrier_Control_initialize(
0100   SMP_barrier_Control *control
0101 )
0102 {
0103   _Atomic_Init_uint( &control->value, 0U );
0104   _Atomic_Init_uint( &control->sense, 0U );
0105 }
0106
0107 /**
0108  * @brief Initializes a SMP barrier per-thread state.
0109  *
0110  * @param[out] state The SMP barrier control.
0111  */
0112 static inline void _SMP_barrier_State_initialize(
0113   SMP_barrier_State *state
0114 )
0115 {
0116   state->sense = 0U;
0117 }
0118
0119 /**
0120  * @brief Waits on the SMP barrier until count threads rendezvoused.
0121  *
0122  * @param[in, out] control The SMP barrier control.
0123  * @param[in, out] state The SMP barrier per-thread state.
0124  * @param count The thread count bound to rendezvous.
0125  *
0126  * @retval true This processor performed the barrier release.
0127  * @retval false This processor did not performe the barrier release.
0128  */
0129 bool _SMP_barrier_Wait(
0130   SMP_barrier_Control *control,
0131   SMP_barrier_State *state,
0132   unsigned int count
0133 );
0134
0135 /**
0136  * @brief Waits until count other threads wait on the SMP barrier to
0137  *   rendezvous.
0138  *
0139  * In contrast to _SMP_barrier_Wait(), this function does not release the
0140  * barrier.
0141  *
0142  * @param[in] control The SMP barrier control.
0143  * @param count The count of other threads.
0144  */
0145 static inline void _SMP_barrier_Wait_for_other(
0146   const SMP_barrier_Control *control,
0147   unsigned int count
0148 )
0149 {
0150   unsigned int value;
0151
0152   do {
0153     value = _Atomic_Load_uint( &control->value, ATOMIC_ORDER_ACQUIRE );
0154   } while ( value != count );
0155 }
0156
0157 /** @} */
0158
0159 #ifdef __cplusplus
0160 }
0161 #endif /* __cplusplus */
0162
0163 #endif /* _RTEMS_SCORE_SMPBARRIER_H */