linux/spi/spidev.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief RTEMS Port of Linux SPI API
0007  *
0008  * @ingroup SPILinux
0009  */
0010
0011 /*
0012  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef _UAPI_LINUX_SPI_H
0037 #define _UAPI_LINUX_SPI_H
0038
0039 #include <sys/ioccom.h>
0040 #include <stddef.h>
0041 #include <stdint.h>
0042
0043 /**
0044  * @defgroup SPILinux Linux SPI User-Space API
0045  *
0046  * @ingroup SPI
0047  *
0048  * @brief RTEMS port of Linux SPI user-space API.
0049  *
0050  * Additional documentation is available through the Linux sources, see
0051  *
0052  * /usr/src/linux/include/uapi/linux/spidev.h.
0053  *
0054  * @{
0055  */
0056
0057 /**
0058  * @name SPI Transfer Flags
0059  *
0060  * @{
0061  */
0062
0063 /**
0064  * @brief SPI transfer flag which sets the clock phase.
0065  */
0066 #define SPI_CPHA 0x01
0067
0068 /**
0069  * @brief SPI transfer flag which sets the clock polarity.
0070  */
0071 #define SPI_CPOL 0x02
0072
0073 /**
0074  * @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
0075  * leading edge).
0076  */
0077 #define SPI_MODE_0 0
0078
0079 /**
0080  * @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
0081  * trailing edge).
0082  */
0083 #define SPI_MODE_1 SPI_CPHA
0084
0085 /**
0086  * @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
0087  * leading edge).
0088  */
0089 #define SPI_MODE_2 SPI_CPOL
0090
0091 /**
0092  * @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
0093  * trailing edge).
0094  */
0095 #define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
0096
0097 /**
0098  * @brief SPI transfer flag which selects the device by setting the chip select
0099  * line.
0100  */
0101 #define SPI_CS_HIGH 0x04
0102
0103 /**
0104  * @brief SPI transfer flag which triggers data transmission with the LSB being
0105  * sent first.
0106  */
0107 #define SPI_LSB_FIRST 0x08
0108
0109 /**
0110  * @brief SPI transfer flag which uses a shared wire for master input/slave
0111  * output as well as master output/slave input.
0112  */
0113 #define SPI_3WIRE 0x10
0114
0115 /**
0116  * @brief SPI transfer flag which initiates the loopback mode.
0117  */
0118 #define SPI_LOOP 0x20
0119
0120 /**
0121  * @brief SPI transfer flag which indicates that no chip select is needed due to
0122  * only one device on the bus.
0123  */
0124 #define SPI_NO_CS 0x40
0125
0126 /**
0127  * @brief SPI transfer flag which pulls the slave to low level during pause.
0128  */
0129 #define SPI_READY 0x80
0130
0131 /**
0132  * @brief SPI transfer flag which sets up dual mode for transmission.
0133  */
0134 #define SPI_TX_DUAL 0x100
0135
0136 /**
0137  * @brief SPI transfer flag which sets up quad mode for transmission.
0138  */
0139 #define SPI_TX_QUAD 0x200
0140
0141 /**
0142  * @brief SPI transfer flag which sets up dual mode for reception.
0143  */
0144 #define SPI_RX_DUAL 0x400
0145
0146 /**
0147  * @brief SPI transfer flag which sets up quad mode for reception.
0148  */
0149 #define SPI_RX_QUAD 0x800
0150
0151 /** @} */
0152
0153 #define SPI_IOC_MAGIC 's'
0154
0155 /**
0156  * @brief SPI transfer message.
0157  */
0158 struct spi_ioc_transfer {
0159   /**
0160    * @brief Buffer for receive data.
0161    */
0162   void *rx_buf;
0163
0164   /**
0165    * @brief Buffer for transmit data.
0166    */
0167   const void *tx_buf;
0168
0169   /**
0170    * @brief Length of receive and transmit buffers in bytes.
0171    */
0172   size_t len;
0173
0174   /**
0175    * @brief Sets the bit-rate of the device.
0176    */
0177   uint32_t speed_hz;
0178
0179   /**
0180    * @brief Sets the delay after a transfer before the chip select status is
0181    * changed and the next transfer is triggered.
0182    */
0183   uint16_t delay_usecs;
0184
0185   /**
0186    * @brief Sets the device wordsize.
0187    */
0188   uint8_t bits_per_word;
0189
0190   /**
0191    * @brief If true, device is deselected after transfer ended and before a new
0192    * transfer is started.
0193    */
0194   uint8_t cs_change;
0195
0196   /**
0197    * @brief Amount of bits that are used for reading.
0198    */
0199   uint8_t rx_nbits;
0200
0201   /**
0202    * @brief Amount of bits that are used for writing.
0203    */
0204   uint8_t tx_nbits;
0205
0206   /**
0207    * @brief Sets one of the possible modes that can be used for SPI transfers
0208    * (dependent on clock phase and polarity).
0209    */
0210   uint32_t mode;
0211
0212   /**
0213    * @brief Indicates which device is currently used.
0214    */
0215   uint8_t cs;
0216 };
0217
0218 /**
0219  * @brief Calculates the size of the SPI message array.
0220  */
0221 #define SPI_MSGSIZE(n) \
0222   (((n) * sizeof(struct spi_ioc_transfer) < IOCPARM_MAX) ? \
0223     (n) * sizeof(struct spi_ioc_transfer) : 0)
0224
0225 /**
0226  * @brief Transfers an array with SPI messages.
0227  */
0228 #define SPI_IOC_MESSAGE(n) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(n)])
0229
0230 /**
0231  * @brief Reads the least-significant 8-bits of the SPI default mode.
0232  */
0233 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, uint8_t)
0234
0235 /**
0236  * @brief Writes the SPI default mode (the most-significant 24-bits of the mode are
0237  * set to zero).
0238  */
0239 #define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, uint8_t)
0240
0241 /**
0242  * @brief Reads the SPI default least-significant bit first setting.
0243  */
0244 #define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, uint8_t)
0245
0246 /**
0247  * @brief Writes the SPI default least-significant-bit first setting.
0248  */
0249 #define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, uint8_t)
0250
0251 /**
0252  * @brief Reads the SPI default bits per word.
0253  */
0254 #define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, uint8_t)
0255
0256 /**
0257  * @brief Writes the SPI default bits per word.
0258  */
0259 #define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, uint8_t)
0260
0261 /**
0262  * @brief Reads the SPI default speed in Hz.
0263  */
0264 #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, uint32_t)
0265
0266 /**
0267  * @brief Writes the SPI default speed in Hz.
0268  */
0269 #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, uint32_t)
0270
0271 /**
0272  * @brief Reads the full 32-bit SPI default mode.
0273  */
0274 #define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, uint32_t)
0275
0276 /**
0277  * @brief Writes the full 32-bit SPI default mode.
0278  */
0279 #define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, uint32_t)
0280
0281 #endif /* _UAPI_LINUX_SPI_H */