include/drvmgr/pci_bus.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @brief PCI bus driver Interface.
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 2008 Cobham Gaisler AB.
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  *
0033  */
0034
0035 /* General part of drvmgr PCI Bus driver. The driver is typically
0036  * initialized from the PCI host driver separating the host
0037  * driver from the common parts in PCI drivers.
0038  * The PCI library must be initialized before starting the
0039  * PCI bus driver. The PCI library have set up BARs and
0040  * assigned system IRQs for targets.
0041  * This PCI bus driver rely on the PCI library (pci.c) for
0042  * interrupt registeration (pci_interrupt_register) and PCI
0043  * target set up.
0044  */
0045
0046 #ifndef __PCI_BUS_H__
0047 #define __PCI_BUS_H__
0048
0049 #include <drvmgr/drvmgr.h>
0050 #include <pci.h>
0051 #include <pci/access.h>
0052
0053 #ifdef __cplusplus
0054 extern "C" {
0055 #endif
0056
0057 /* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */
0058 #define DRIVER_PCI_ID(vendor, device) \
0059     DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \
0060         ((((vendor) & 0xffff) << 16) | ((device) & 0xffff)))
0061
0062 /* PCI Driver ID generation (CLASS: 24-bit) */
0063 #define DRIVER_PCI_CLASS(class) \
0064     DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff)))
0065
0066 /* PCI driver IDs  (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */
0067 #define DRIVER_PCI_GAISLER_RASTAIO_ID       DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO)
0068 #define DRIVER_PCI_GAISLER_RASTATMTC_ID     DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC)
0069 #define DRIVER_PCI_GAISLER_GR701_ID     DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701)
0070 #define DRIVER_PCI_GAISLER_RASTAADCDAC_ID   DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC)
0071 #define DRIVER_PCI_GAISLER_TMTC_1553_ID     DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553)
0072 #define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID  DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR)
0073 #define DRIVER_PCI_GAISLER_LEON4_N2X_ID     DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X)
0074 #define DRIVER_PCI_GAISLER_CPCI_GR740_ID    DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_CPCI_GR740)
0075
0076 struct pci_dev_id {
0077     uint16_t        vendor;
0078     uint16_t        device;
0079     uint16_t        subvendor;
0080     uint16_t        subdevice;
0081     uint32_t        class; /* 24 lower bits */
0082 };
0083
0084 struct pci_dev_id_match {
0085     uint16_t        vendor;
0086     uint16_t        device;
0087     uint16_t        subvendor;
0088     uint16_t        subdevice;
0089     uint32_t        class;  /* 24 lower bits */
0090     uint32_t        class_mask; /* 24 lower bits */
0091 };
0092 #define PCIID_DEVVEND(vendor, device) \
0093     {vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0}
0094 #define PCIID_END_TABLE {0, 0, 0, 0, 0, 0}
0095
0096 enum {
0097     /* A Device has up to 6 BARs and an optional ROM BAR */
0098     PCIDEV_RES_BAR1 = 0,
0099     PCIDEV_RES_BAR2 = 1,
0100     PCIDEV_RES_BAR3 = 2,
0101     PCIDEV_RES_BAR4 = 3,
0102     PCIDEV_RES_BAR5 = 4,
0103     PCIDEV_RES_BAR6 = 5,
0104     PCIDEV_RES_ROM  = 6,
0105 };
0106 /* Maximum Number of Resources of a device */
0107 #define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1)
0108
0109 /* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */
0110 struct pcibus_res {
0111     uint32_t        address; /* Base Address, CPU accessible */
0112     uint32_t        size;    /* 0=Unimplemented, 0!=Resource Size */
0113     struct pci_res      *res;    /* PCI-layer resource */
0114 };
0115
0116 struct pci_dev_info {
0117     struct pci_dev_id   id;
0118     uint8_t         rev;
0119     uint8_t         irq; /* 0 = NO IRQ */
0120     pci_dev_t       pcidev;
0121     struct pcibus_res   resources[PCIDEV_RES_CNT];
0122     struct pci_dev      *pci_device;
0123 };
0124
0125 struct pci_drv_info {
0126     struct drvmgr_drv   general;    /* General bus info */
0127     /* PCI specific bus information */
0128     struct pci_dev_id_match     *ids;       /* Supported hardware */
0129 };
0130
0131 /* Access routines */
0132 struct pcibus_regmem_ops {
0133     drvmgr_r8 r8;
0134     drvmgr_r16 r16;
0135     drvmgr_r32 r32;
0136     drvmgr_r64 r64;
0137     drvmgr_w8 w8;
0138     drvmgr_w16 w16;
0139     drvmgr_w32 w32;
0140     drvmgr_w64 w64;
0141 };
0142
0143 /* Let driver configure PCI bus driver */
0144 struct pcibus_config {
0145     struct drvmgr_map_entry     *maps_up;
0146     struct drvmgr_map_entry     *maps_down;
0147 };
0148
0149 /* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */
0150 #define PCI_FUNC_CFG_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG)
0151 #define PCI_FUNC_CFG_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG)
0152 #define PCI_FUNC_CFG_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG)
0153 #define PCI_FUNC_CFG_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG)
0154 #define PCI_FUNC_CFG_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG)
0155 #define PCI_FUNC_CFG_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG)
0156
0157 /* PCI I/O Register Access - Not implemented (use PCI Lib directly) */
0158 #define PCI_FUNC_IO_R8    DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO)
0159 #define PCI_FUNC_IO_R16   DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO)
0160 #define PCI_FUNC_IO_R32   DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO)
0161 #define PCI_FUNC_IO_W8    DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO)
0162 #define PCI_FUNC_IO_W16   DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO)
0163 #define PCI_FUNC_IO_W32   DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO)
0164
0165 /* PCI Register Access over Memory Space (Little Endian) */
0166 #define PCI_FUNC_MREG_R8   DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG)
0167 #define PCI_FUNC_MREG_R16  DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE)
0168 #define PCI_FUNC_MREG_R32  DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE)
0169 #define PCI_FUNC_MREG_W8   DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG)
0170 #define PCI_FUNC_MREG_W16  DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE)
0171 #define PCI_FUNC_MREG_W32  DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE)
0172
0173 /* Weak default PCI driver resources, override this from project configuration
0174  * to set PCI Bus resources used to configure PCI device drivers.
0175  */
0176 extern struct drvmgr_bus_res pcibus_drv_resources;
0177
0178 /* Attach a PCI bus on top of a PCI Host device */
0179 extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg);
0180
0181 #ifdef __cplusplus
0182 }
0183 #endif
0184
0185 #endif