dev/i2c/xilinx-axi-i2c.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org>  All rights reserved.
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 /*
0029  * Xilinx AXI IIC Interface v2.0. See PG090.pdf.
0030  *
0031  * Note, only master support is provided and no dynamic mode by design.
0032  *
0033  * The clock set up is to be handled by the IP integrator. There are too many
0034  * factors handling this in software.
0035  */
0036
0037
0038 #ifndef XILINX_AXI_I2C_H
0039 #define XILINX_AXI_I2C_H
0040
0041 #include <dev/i2c/i2c.h>
0042
0043 /*
0044  * The PL integrator controls the timing. This interface allows software to
0045  * override those settings. It pays to check the timing with ChipScope.
0046  *
0047  * If you set the AXI bus frequency you can use the clock speed ioctl call to
0048  * change the speed dymanically. The ioctl call overrides the defaults passed
0049  * in.
0050  *
0051  * Set the valid mask to the values that are to be set.
0052  */
0053 #define XILINX_AIX_I2C_AXI_CLOCK (1 << 0)
0054 #define XILINX_AIX_I2C_TSUSTA    (1 << 1)
0055 #define XILINX_AIX_I2C_TSUSTO    (1 << 2)
0056 #define XILINX_AIX_I2C_THDSTA    (1 << 3)
0057 #define XILINX_AIX_I2C_TSUDAT    (1 << 4)
0058 #define XILINX_AIX_I2C_TBUF      (1 << 5)
0059 #define XILINX_AIX_I2C_THIGH     (1 << 6)
0060 #define XILINX_AIX_I2C_TLOW      (1 << 7)
0061 #define XILINX_AIX_I2C_THDDAT    (1 << 8)
0062 #define XILINX_AIX_I2C_ALL_REGS  (XILINX_AIX_I2C_TSUSTA | \
0063                                   XILINX_AIX_I2C_TSUSTO | \
0064                                   XILINX_AIX_I2C_THDSTA | \
0065                                   XILINX_AIX_I2C_TSUDAT | \
0066                                   XILINX_AIX_I2C_TBUF   | \
0067                                   XILINX_AIX_I2C_THIGH  | \
0068                                   XILINX_AIX_I2C_TLOW   | \
0069                                   XILINX_AIX_I2C_THDDAT)
0070 typedef struct
0071 {
0072   uint32_t valid_mask;
0073   uint32_t AXI_CLOCK;
0074   uint32_t SCL_INERTIAL_DELAY;
0075   uint32_t TSUSTA;
0076   uint32_t TSUSTO;
0077   uint32_t THDSTA;
0078   uint32_t TSUDAT;
0079   uint32_t TBUF;
0080   uint32_t THIGH;
0081   uint32_t TLOW;
0082   uint32_t THDDAT;
0083 } xilinx_aix_i2c_timing;
0084
0085 /*
0086  * Register the driver.
0087  *
0088  * The driver can multipex a number of I2C buses (in master mode only) using
0089  * the GPO port. The PL designer can use the output pins to select a bus. This
0090  * is useful if connecting a number of slave devices that have limit selectable
0091  * addresses.
0092  *
0093  * @param bus_path The driver's device path.
0094  * @param register_base AXI base address.
0095  * @param irq AXI FPGA interrupt.
0096  * @param gpio_address Bits 12:15 of a slave address it written to the GPO.
0097  * @param timing Override the default timing. NULL means no changes.
0098  */
0099 int i2c_bus_register_xilinx_aix_i2c(const char*                  bus_path,
0100                                     uintptr_t                    register_base,
0101                                     rtems_vector_number          irq,
0102                                     bool                         ten_gpio,
0103                                     const xilinx_aix_i2c_timing* timing);
0104
0105 #endif