dev/serial/sc16is752-regs.h

0001 /*
0002  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0003  *
0004  * The license and distribution terms for this file may be
0005  * found in the file LICENSE in this distribution or at
0006  * http://www.rtems.org/license/LICENSE.
0007  */
0008
0009 #ifndef LIBBSP_ARM_ATSAM_SC16IS752_H
0010 #define LIBBSP_ARM_ATSAM_SC16IS752_H
0011
0012 #ifdef __cplusplus
0013 extern "C" {
0014 #endif /* __cplusplus */
0015
0016 /* General register set */
0017 #define SC16IS752_RHR 0x0
0018 #define SC16IS752_THR 0x0
0019 #define SC16IS752_IER 0x1
0020 #define SC16IS752_FCR 0x2
0021 #define SC16IS752_IIR 0x2
0022 #define SC16IS752_LCR 0x3
0023 #define SC16IS752_MCR 0x4
0024 #define SC16IS752_LSR 0x5
0025 #define SC16IS752_MSR 0x6
0026 #define SC16IS752_TCR 0x6
0027 #define SC16IS752_SPR 0x7
0028 #define SC16IS752_TLR 0x7
0029 #define SC16IS752_TXLVL 0x8
0030 #define SC16IS752_RXLVL 0x9
0031 #define SC16IS752_IODIR 0xA
0032 #define SC16IS752_IOSTATE 0xB
0033 #define SC16IS752_IOINTENA 0xC
0034 #define SC16IS752_IOCONTROL 0xE
0035 #define SC16IS752_EFCR 0xF
0036
0037 /* Special register set */
0038 #define SC16IS752_DLL 0x0
0039 #define SC16IS752_DLH 0x1
0040
0041 /* Enhanced register set */
0042 #define SC16IS752_EFR 0x2
0043 #define SC16IS752_XON1 0x4
0044 #define SC16IS752_XON2 0x5
0045 #define SC16IS752_XOFF1 0x6
0046 #define SC16IS752_XOFF2 0x7
0047
0048 /* FCR */
0049 #define SC16IS752_FCR_FIFO_EN        0x01
0050 #define SC16IS752_FCR_RX_FIFO_RST    0x02
0051 #define SC16IS752_FCR_TX_FIFO_RST    0x04
0052 #define SC16IS752_FCR_TX_FIFO_TRG_8  0x00
0053 #define SC16IS752_FCR_TX_FIFO_TRG_16 0x10
0054 #define SC16IS752_FCR_TX_FIFO_TRG_32 0x20
0055 #define SC16IS752_FCR_TX_FIFO_TRG_56 0x30
0056 #define SC16IS752_FCR_RX_FIFO_TRG_8  0x00
0057 #define SC16IS752_FCR_RX_FIFO_TRG_16 0x40
0058 #define SC16IS752_FCR_RX_FIFO_TRG_56 0x80
0059 #define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0
0060
0061 /* EFCR */
0062 #define SC16IS752_EFCR_RS485_ENABLE (1u << 0)
0063 #define SC16IS752_EFCR_RX_DISABLE (1u << 1)
0064 #define SC16IS752_EFCR_TX_DISABLE (1u << 2)
0065 #define SC16IS752_EFCR_RTSCON (1u << 4)
0066 #define SC16IS752_EFCR_RTSINVER (1u << 5)
0067
0068 /* IER */
0069 #define SC16IS752_IER_RHR (1u << 0)
0070 #define SC16IS752_IER_THR (1u << 1)
0071 #define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2)
0072 #define SC16IS752_IER_MODEM_STATUS (1u << 3)
0073 #define SC16IS752_IER_SLEEP_MODE (1u << 4)
0074 #define SC16IS752_IER_XOFF (1u << 5)
0075 #define SC16IS752_IER_RTS (1u << 6)
0076 #define SC16IS752_IER_CTS (1u << 7)
0077
0078 /* IIR */
0079 #define SC16IS752_IIR_TX_INTERRUPT (1u << 1)
0080 #define SC16IS752_IIR_RX_INTERRUPT (1u << 2)
0081
0082 /* LCR */
0083 #define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
0084 #define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
0085 #define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
0086 #define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
0087 #define SC16IS752_LCR_2_STOP_BIT (1u << 2)
0088 #define SC16IS752_LCR_SET_PARITY (1u << 3)
0089 #define SC16IS752_LCR_EVEN_PARITY (1u << 4)
0090 #define SC16IS752_LCR_BREAK (1u << 5)
0091 #define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)
0092
0093 /* LSR */
0094 #define SC16IS752_LSR_TXEMPTY (1u << 5)
0095 #define SC16IS752_LSR_RXRDY (1u << 0)
0096 #define SC16IS752_LSR_ERROR_BITS (7u << 2)
0097
0098 /* MCR */
0099 #define SC16IS752_MCR_DTR             (1u << 0)
0100 #define SC16IS752_MCR_RTS             (1u << 1)
0101 #define SC16IS752_MCR_TCR_TLR         (1u << 2)
0102 #define SC16IS752_MCR_LOOPBACK        (1u << 4)
0103 #define SC16IS752_MCR_XON_ANY         (1u << 5)
0104 #define SC16IS752_MCR_IRDA_ENABLE     (1u << 6)
0105 #define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)
0106
0107 /* MSR */
0108 #define SC16IS752_MSR_dCTS (1u << 0)
0109 #define SC16IS752_MSR_dDSR (1u << 1)
0110 #define SC16IS752_MSR_dRI  (1u << 2)
0111 #define SC16IS752_MSR_dCD  (1u << 3)
0112 #define SC16IS752_MSR_CTS  (1u << 4)
0113 #define SC16IS752_MSR_DSR  (1u << 5)
0114 #define SC16IS752_MSR_RI   (1u << 6)
0115 #define SC16IS752_MSR_CD   (1u << 7)
0116
0117 /* EFR */
0118 #define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4)
0119 #define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5)
0120 #define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)
0121 #define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)
0122
0123 /* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */
0124
0125 #define SC16IS752_FIFO_DEPTH 64
0126
0127 #ifdef __cplusplus
0128 }
0129 #endif /* __cplusplus */
0130
0131 #endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */