amd64/interrupts/pic.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsX8664AMD64
0007  *
0008  * @brief PIC remap and disable implementation
0009  */
0010
0011 /*
0012  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0024  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0027  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0028  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0029  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0030  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0031  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0032  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0033  * SUCH DAMAGE.
0034  */
0035
0036 #include <stdint.h>
0037 #include <rtems.h>
0038 #include <rtems/score/basedefs.h>
0039 #include <rtems/score/x86_64.h>
0040 #include <rtems/score/cpuimpl.h>
0041 #include <bsp/irq-generic.h>
0042 #include <pic.h>
0043
0044 void pic_remap(uint8_t offset1, uint8_t offset2)
0045 {
0046   uint8_t a1, a2;
0047
0048   /* save masks */
0049   a1 = inport_byte(PIC1_DATA);
0050   a2 = inport_byte(PIC2_DATA);
0051
0052   /* start the initialization sequence in cascade mode */
0053   outport_byte(PIC1_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
0054   stub_io_wait();
0055   outport_byte(PIC2_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
0056   stub_io_wait();
0057   /* ICW2: Master PIC vector offset */
0058   outport_byte(PIC1_DATA, offset1);
0059   stub_io_wait();
0060   /* ICW2: Slave PIC vector offset */
0061   outport_byte(PIC2_DATA, offset2);
0062   stub_io_wait();
0063   /* ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100) */
0064   outport_byte(PIC1_DATA, 4);
0065   stub_io_wait();
0066   /* ICW3: tell Slave PIC its cascade identity (0000 0010) */
0067   outport_byte(PIC2_DATA, 2);
0068   stub_io_wait();
0069
0070   outport_byte(PIC1_DATA, PIC_ICW4_8086);
0071   stub_io_wait();
0072   outport_byte(PIC2_DATA, PIC_ICW4_8086);
0073   stub_io_wait();
0074
0075   /* restore saved masks. */
0076   outport_byte(PIC1_DATA, a1);
0077   outport_byte(PIC2_DATA, a2);
0078 }
0079
0080 void pic_disable(void)
0081 {
0082   /* Mask all lines on both master and slave PIC to disable */
0083   outport_byte(PIC1_DATA, 0xff);
0084   outport_byte(PIC2_DATA, 0xff);
0085 }