amd64/include/pic.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsX8664AMD64
0007  *
0008  * @brief PIC definitions
0009  */
0010
0011 /*
0012  * Copyright (c) 2018 Amaan Cheval <amaan.cheval@gmail.com>
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0024  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0027  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0028  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0029  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0030  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0031  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0032  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0033  * SUCH DAMAGE.
0034  */
0035
0036 #ifndef _AMD64_PIC_H
0037 #define _AMD64_PIC_H
0038
0039 #ifdef __cplusplus
0040 extern "C" {
0041 #endif
0042
0043 #define PIC1          0x20  /* IO base address for master PIC */
0044 #define PIC2          0xA0  /* IO base address for slave PIC */
0045 #define PIC1_COMMAND  PIC1
0046 #define PIC1_DATA    (PIC1+1)
0047 #define PIC2_COMMAND  PIC2
0048 #define PIC2_DATA    (PIC2+1)
0049
0050 /* reinitialize the PIC controllers, giving them specified vector offsets
0051    rather than 8h and 70h, as configured by default */
0052
0053 #define PIC_ICW1_ICW4       0x01  /* ICW4 (not) needed */
0054 #define PIC_ICW1_SINGLE     0x02  /* Single (cascade) mode */
0055 #define PIC_ICW1_INTERVAL4  0x04  /* Call address interval 4 (8) */
0056 #define PIC_ICW1_LEVEL      0x08  /* Level triggered (edge) mode */
0057 #define PIC_ICW1_INIT       0x10  /* Initialization - required! */
0058
0059 #define PIC_ICW4_8086       0x01  /* 8086/88 (MCS-80/85) mode */
0060 #define PIC_ICW4_AUTO       0x02  /* Auto (normal) EOI */
0061 #define PIC_ICW4_BUF_SLAVE  0x08  /* Buffered mode/slave */
0062 #define PIC_ICW4_BUF_MASTER 0x0C  /* Buffered mode/master */
0063 #define PIC_ICW4_SFNM       0x10  /* Special fully nested (not) */
0064
0065 /* This remaps IRQ0 to vector number 0x20 and so on (i.e. IDT[32]) */
0066 #define PIC1_REMAP_DEST           0x20
0067 #define PIC2_REMAP_DEST           0x28
0068
0069 /* Remap PIC1's interrupts to offset1 and PIC2's to offset2 */
0070 void pic_remap(uint8_t offset1, uint8_t offset2);
0071
0072 /**
0073  * Mask all interrupt requests on PIC.
0074  *
0075  * @note Even with all interrupts masked, the PIC may still send spurious
0076  * interrupts (IRQ7), so we should handle them still.
0077  */
0078 void pic_disable(void);
0079
0080 #ifdef __cplusplus
0081 }
0082 #endif
0083
0084 #endif /* _AMD64_PIC_H */