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0001 niagara
0002 =======
0003 ```
0004 BSP NAME: niagara
0005 BOARD:
0006 BUS: n/a
0007 CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v)
0008 CPU: UltraSPARC T1 (OpenSPARC T1)
0009 COPROCESSORS:
0010 MODE: n/a
0011
0012 DEBUG MONITOR:
0013 ```
0014
0015 PERIPHERALS
0016 -----------
0017 ```
0018 TIMERS: TICK and STICK registers (ASRs 4 and 24)
0019 RESOLUTION: CPU clock resolution
0020 SERIAL PORTS:
0021 REAL-TIME CLOCK:
0022 DMA: none
0023 VIDEO: none
0024 SCSI: none
0025 NETWORKING: none
0026 ```
0027
0028 DRIVER INFORMATION
0029 ------------------
0030 ```
0031 CLOCK DRIVER:
0032 IOSUPP DRIVER:
0033 SHMSUPP:
0034 TIMER DRIVER:
0035 TTY DRIVER:
0036 ```
0037
0038 STDIO
0039 -----
0040 ```
0041 PORT:
0042 ELECTRICAL:
0043 BAUD:
0044 BITS PER CHARACTER:
0045 PARITY:
0046 STOP BITS:
0047 ```
0048
0049
0050 Board description
0051 -----------------
0052 ```
0053 clock rate:
0054 bus width:
0055 ROM:
0056 RAM:
0057 ```
0058
0059 This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64
0060 and similar processors.
0061
0062 This BSP has been run on the Simics simulator with the niagara target, which
0063 simulates the OpenSPARC T1 Niagara implementation.
0064
0065 This BSP has been run on the M5 simulator with the SPARC_FS target, which
0066 simulates the OpenSPARC T1 Niagara implementation.
0067
0068 Simics:
0069 A commercially available simulator licensed by Virtutech.
0070 https://www.simics.net/
0071
0072 M5:
0073 An open-source simulator.
0074 http://www.m5sim.org/wiki/index.php/Main_Page
