mm/sun4u/mmu.h

0001 /*
0002  * Copyright (c) 2005 Jakub Jermar
0003  * All rights reserved.
0004  *
0005  * Redistribution and use in source and binary forms, with or without
0006  * modification, are permitted provided that the following conditions
0007  * are met:
0008  *
0009  * - Redistributions of source code must retain the above copyright
0010  *   notice, this list of conditions and the following disclaimer.
0011  * - Redistributions in binary form must reproduce the above copyright
0012  *   notice, this list of conditions and the following disclaimer in the
0013  *   documentation and/or other materials provided with the distribution.
0014  * - The name of the author may not be used to endorse or promote products
0015  *   derived from this software without specific prior written permission.
0016  *
0017  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
0018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
0019  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0020  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0022  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0023  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0024  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0025  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0026  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0027  */
0028
0029 /** @addtogroup RTEMSBSPsSPARC64mm
0030  * @{
0031  */
0032 /** @file
0033  */
0034
0035 #ifndef KERN_sparc64_sun4u_MMU_H_
0036 #define KERN_sparc64_sun4u_MMU_H_
0037
0038 #if defined(US)
0039 /* LSU Control Register ASI. */
0040 #define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
0041 #endif
0042
0043 /* I-MMU ASIs. */
0044 #define ASI_IMMU            0x50
0045 #define ASI_IMMU_TSB_8KB_PTR_REG    0x51
0046 #define ASI_IMMU_TSB_64KB_PTR_REG   0x52
0047 #define ASI_ITLB_DATA_IN_REG        0x54
0048 #define ASI_ITLB_DATA_ACCESS_REG    0x55
0049 #define ASI_ITLB_TAG_READ_REG       0x56
0050 #define ASI_IMMU_DEMAP          0x57
0051
0052 /* Virtual Addresses within ASI_IMMU. */
0053 #define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
0054 #define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
0055 #define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
0056 #define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
0057 #if defined (US3)
0058 #define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
0059 #define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
0060 #endif
0061
0062
0063 /* D-MMU ASIs. */
0064 #define ASI_DMMU            0x58
0065 #define ASI_DMMU_TSB_8KB_PTR_REG    0x59
0066 #define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
0067 #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
0068 #define ASI_DTLB_DATA_IN_REG        0x5c
0069 #define ASI_DTLB_DATA_ACCESS_REG    0x5d
0070 #define ASI_DTLB_TAG_READ_REG       0x5e
0071 #define ASI_DMMU_DEMAP          0x5f
0072
0073 /* Virtual Addresses within ASI_DMMU. */
0074 #define VA_DMMU_TSB_TAG_TARGET      0x0 /**< DMMU TSB tag target register. */
0075 #define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
0076 #define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
0077 #define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
0078 #define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
0079 #define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
0080 #define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
0081 #define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
0082 #define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
0083 #if defined (US3)
0084 #define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
0085 #define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
0086 #define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
0087 #endif
0088
0089 #ifndef __ASM__
0090
0091 #include <arch/asm.h>
0092 #include <arch/barrier.h>
0093 #include <arch/types.h>
0094
0095 #if defined(US)
0096 /** LSU Control Register. */
0097 typedef union {
0098     uint64_t value;
0099     struct {
0100         unsigned : 23;
0101         unsigned pm : 8;
0102         unsigned vm : 8;
0103         unsigned pr : 1;
0104         unsigned pw : 1;
0105         unsigned vr : 1;
0106         unsigned vw : 1;
0107         unsigned : 1;
0108         unsigned fm : 16;
0109         unsigned dm : 1;    /**< D-MMU enable. */
0110         unsigned im : 1;    /**< I-MMU enable. */
0111         unsigned dc : 1;    /**< D-Cache enable. */
0112         unsigned ic : 1;    /**< I-Cache enable. */
0113
0114     } __attribute__ ((packed));
0115 } lsu_cr_reg_t;
0116 #endif /* US */
0117
0118 #endif /* !def __ASM__ */
0119
0120 #endif
0121
0122 /** @}
0123  */