leon3/include/tm27.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup RTEMSBSPsSPARCLEON3
0006  * @brief Implementations for interrupt mechanisms for Time Test 27
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 2006.
0011  *  Aeroflex Gaisler AB.
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef _RTEMS_TMTEST27
0036 #error "This is an RTEMS internal file you must not include directly."
0037 #endif
0038
0039 #ifndef __tm27_h
0040 #define __tm27_h
0041
0042 #include <bsp.h>
0043 #include <bsp/irq-generic.h>
0044
0045 #if defined(RTEMS_SMP)
0046 #include <rtems/score/smpimpl.h>
0047 #endif
0048
0049 /*
0050  *  Define the interrupt mechanism for Time Test 27
0051  *
0052  *  NOTE: Since the interrupt code for the SPARC supports both synchronous
0053  *        and asynchronous trap handlers, support for testing with both
0054  *        is included.
0055  */
0056
0057 #define SIS_USE_SYNCHRONOUS_TRAP  0
0058
0059 /*
0060  *  The synchronous trap is an arbitrarily chosen software trap.
0061  */
0062
0063 #if (SIS_USE_SYNCHRONOUS_TRAP == 1)
0064
0065 #define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
0066
0067 #define MUST_WAIT_FOR_INTERRUPT 1
0068
0069 #define TM27_USE_VECTOR_HANDLER
0070
0071 #define Install_tm27_vector( handler ) \
0072   set_vector( (handler), TEST_VECTOR, 1 );
0073
0074 #define Cause_tm27_intr() \
0075   __asm__ volatile( "ta 0x10; nop " );
0076
0077 #define Clear_tm27_intr() /* empty */
0078
0079 #define Lower_tm27_intr() /* empty */
0080
0081 /*
0082  *  The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
0083  */
0084
0085 #else   /* use a regular asynchronous trap */
0086
0087 extern uint32_t Interrupt_nest;
0088
0089 #define TEST_INTERRUPT_SOURCE 5
0090 #define TEST_INTERRUPT_SOURCE2 6
0091 #define MUST_WAIT_FOR_INTERRUPT 1
0092 #define TM27_INTERRUPT_VECTOR_DEFAULT TEST_INTERRUPT_SOURCE
0093
0094 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0095 {
0096   static rtems_interrupt_entry entry_low;
0097   static rtems_interrupt_entry entry_high;
0098
0099 #if defined(RTEMS_SMP)
0100   bsp_interrupt_set_affinity(
0101     TEST_INTERRUPT_SOURCE,
0102     _SMP_Get_online_processors()
0103   );
0104   bsp_interrupt_set_affinity(
0105     TEST_INTERRUPT_SOURCE2,
0106     _SMP_Get_online_processors()
0107   );
0108 #endif
0109
0110   rtems_interrupt_entry_initialize(
0111     &entry_low,
0112     handler,
0113     NULL,
0114     "tm27 low"
0115   );
0116   (void) rtems_interrupt_entry_install(
0117     TEST_INTERRUPT_SOURCE,
0118     RTEMS_INTERRUPT_SHARED,
0119     &entry_low
0120   );
0121   rtems_interrupt_entry_initialize(
0122     &entry_high,
0123     handler,
0124     NULL,
0125     "tm27 high"
0126   );
0127   (void) rtems_interrupt_entry_install(
0128     TEST_INTERRUPT_SOURCE2,
0129     RTEMS_INTERRUPT_SHARED,
0130     &entry_high
0131   );
0132 }
0133
0134 static inline void Cause_tm27_intr( void )
0135 {
0136   rtems_vector_number vector;
0137
0138   vector = TEST_INTERRUPT_SOURCE + ( Interrupt_nest >> 1 );
0139 #if defined(RTEMS_SMP)
0140   (void) rtems_interrupt_raise_on( vector, rtems_scheduler_get_processor() );
0141 #else
0142   (void) rtems_interrupt_raise( vector );
0143 #endif
0144   nop();
0145   nop();
0146   nop();
0147 }
0148
0149 static inline void Clear_tm27_intr( void )
0150 {
0151   (void) rtems_interrupt_clear( TEST_INTERRUPT_SOURCE );
0152 }
0153
0154 #define Lower_tm27_intr() /* empty */
0155
0156 #endif
0157
0158 #endif