leon3/include/leon.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup RTEMSBSPsSPARCLEON3
0006  * @brief LEON3 BSP data types and macros
0007  */
0008
0009 /*  leon.h
0010  *
0011  *  LEON3 BSP data types and macros.
0012  *
0013  *  COPYRIGHT (c) 1989-1998.
0014  *  On-Line Applications Research Corporation (OAR).
0015  *
0016  *  Modified for LEON3 BSP.
0017  *  COPYRIGHT (c) 2004.
0018  *  Gaisler Research.
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #ifndef _INCLUDE_LEON_h
0043 #define _INCLUDE_LEON_h
0044
0045 #include <rtems.h>
0046 #include <amba.h>
0047 #include <grlib/io.h>
0048 #include <bsp/leon3.h>
0049
0050 #ifdef __cplusplus
0051 extern "C" {
0052 #endif
0053
0054 #define LEON_INTERRUPT_EXTERNAL_1 5
0055
0056 #ifndef ASM
0057 /*
0058  *  Trap Types for on-chip peripherals
0059  *
0060  *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
0061  *
0062  *  NOTE: The priority level for each source corresponds to the least
0063  *        significant nibble of the trap type.
0064  */
0065
0066 #define LEON_TRAP_TYPE( _source ) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source )
0067
0068 #define LEON_TRAP_SOURCE( _trap ) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap )
0069
0070 #define LEON_INT_TRAP( _trap ) SPARC_IS_INTERRUPT_TRAP( _trap )
0071
0072 /* /\* */
0073 /*  *  This is used to manipulate the on-chip registers. */
0074 /*  * */
0075 /*  *  The following symbol must be defined in the linkcmds file and point */
0076 /*  *  to the correct location. */
0077 /*  *\/ */
0078 /* Leon uses dynamic register mapping using amba configuration records */
0079 /* LEON_Register_Map is obsolete */
0080 /* extern LEON_Register_Map LEON_REG; */
0081
0082 #endif
0083
0084 /*
0085  *  The following defines the bits in Memory Configuration Register 1.
0086  */
0087
0088 #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
0089
0090 /*
0091  *  The following defines the bits in Memory Configuration Register 1.
0092  */
0093
0094 #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
0095
0096
0097 /*
0098  *  The following defines the bits in the Timer Control Register.
0099  */
0100
0101 #define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
0102                                               /* 0 = hold scalar and counter */
0103 #define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
0104                                               /* 0 = stop at 0 */
0105 #define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
0106                                               /* 0 = no function */
0107
0108 /*
0109  *  The following defines the bits in the UART Control Registers.
0110  */
0111
0112 #define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
0113
0114 /*
0115  *  The following defines the bits in the LEON UART Status Register.
0116  */
0117
0118 #define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
0119 #define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
0120 #define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
0121 #define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
0122 #define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
0123 #define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
0124 #define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
0125 #define LEON_REG_UART_STATUS_TF   0x00000200 /* FIFO Full */
0126 #define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
0127
0128 /*
0129  *  The following defines the bits in the LEON UART Control Register.
0130  */
0131
0132 #define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
0133 #define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
0134 #define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
0135 #define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
0136 #define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
0137 #define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
0138 #define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
0139 #define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
0140 #define LEON_REG_UART_CTRL_DB     0x00000800 /* Debug FIFO enable */
0141 #define LEON_REG_UART_CTRL_SI     0x00004000 /* TX shift register empty IRQ enable */
0142 #define LEON_REG_UART_CTRL_FA     0x80000000 /* FIFO Available */
0143 #define LEON_REG_UART_CTRL_FA_BIT 31
0144
0145 /* Macros used for manipulating bits in LEON3 GP Timer Control Register */
0146
0147 #define LEON3_IRQMPSTATUS_CPUNR     28
0148 #define LEON3_IRQMPSTATUS_BROADCAST 27
0149
0150
0151 #ifndef ASM
0152
0153 /*
0154  *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
0155  *  and the Interrupt Pending Registers.
0156  *
0157  *  NOTE: For operations which are not atomic, this code disables interrupts
0158  *        to guarantee there are no intervening accesses to the same register.
0159  *        The operations which read the register, modify the value and then
0160  *        store the result back are vulnerable.
0161  */
0162
0163 #define LEON_Clear_interrupt( _source ) \
0164   grlib_store_32(&LEON3_IrqCtrl_Regs->iclear, 1U << (_source))
0165
0166 #define LEON_Force_interrupt( _source ) \
0167   grlib_store_32(&LEON3_IrqCtrl_Regs->iforce0, 1U << (_source))
0168
0169 #define LEON_Enable_interrupt_broadcast( _source ) \
0170   do { \
0171     rtems_interrupt_lock_context _lock_context; \
0172     uint32_t _mask = 1U << ( _source ); \
0173     uint32_t _brdcst; \
0174     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0175     _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \
0176     _brdcst |= _mask; \
0177     grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \
0178     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0179   } while (0)
0180
0181 #define LEON_Disable_interrupt_broadcast( _source ) \
0182   do { \
0183     rtems_interrupt_lock_context _lock_context; \
0184     uint32_t _mask = 1U << ( _source ); \
0185     uint32_t _brdcst; \
0186     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0187     _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \
0188     _brdcst &= ~_mask; \
0189     grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \
0190     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0191   } while (0)
0192
0193 #define LEON_Is_interrupt_pending( _source ) \
0194   (grlib_load_32(&LEON3_IrqCtrl_Regs->ipend) & (1U << (_source)))
0195
0196 #define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \
0197      (!(grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu]) & (1U << (_source))))
0198
0199 #define LEON_Cpu_Mask_interrupt( _source, _cpu ) \
0200   do { \
0201     rtems_interrupt_lock_context _lock_context; \
0202     uint32_t _pimask; \
0203     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0204     _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \
0205     _pimask &= ~(1U << (_source)); \
0206     grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \
0207     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0208   } while (0)
0209
0210 #define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \
0211   do { \
0212     rtems_interrupt_lock_context _lock_context; \
0213     uint32_t _pimask; \
0214     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0215     _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \
0216     _pimask |= 1U << (_source); \
0217     grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \
0218     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0219   } while (0)
0220
0221 #define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \
0222   do { \
0223     rtems_interrupt_lock_context _lock_context; \
0224     uint32_t _mask = 1U << (_source); \
0225     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0226     (_previous) = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \
0227     grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], (_previous) & ~_mask); \
0228     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0229     (_previous) &= _mask; \
0230   } while (0)
0231
0232 #define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \
0233   do { \
0234     rtems_interrupt_lock_context _lock_context; \
0235     uint32_t _pimask; \
0236     LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \
0237     _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \
0238     _pimask &= ~(1U << (_source)); \
0239     _pimask |= _previous; \
0240     grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \
0241     LEON3_IRQCTRL_RELEASE( &_lock_context ); \
0242   } while (0)
0243
0244 /* Map single-cpu operations to local CPU */
0245 #define LEON_Is_interrupt_masked( _source ) \
0246   LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor())
0247
0248 #define LEON_Mask_interrupt(_source) \
0249   LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor())
0250
0251 #define LEON_Unmask_interrupt(_source) \
0252   LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor())
0253
0254 #define LEON_Disable_interrupt(_source, _previous) \
0255   LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor())
0256
0257 #define LEON_Restore_interrupt(_source, _previous) \
0258   LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor())
0259
0260 /* Make all SPARC BSPs have common macros for interrupt handling */
0261 #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
0262 #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
0263 #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
0264 #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
0265 #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
0266 #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
0267 #define BSP_Disable_interrupt(_source, _previous) \
0268         LEON_Disable_interrupt(_source, _prev)
0269 #define BSP_Restore_interrupt(_source, _previous) \
0270         LEON_Restore_interrupt(_source, _previous)
0271
0272 /* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
0273 #define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
0274         LEON_Cpu_Is_interrupt_masked(_source, _cpu)
0275 #define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
0276         LEON_Cpu_Unmask_interrupt(_source, _cpu)
0277 #define BSP_Cpu_Mask_interrupt(_source, _cpu) \
0278         LEON_Cpu_Mask_interrupt(_source, _cpu)
0279 #define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
0280         LEON_Cpu_Disable_interrupt(_source, _prev, _cpu)
0281 #define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
0282         LEON_Cpu_Restore_interrupt(_source, _previous, _cpu)
0283
0284 /*
0285  *  Each timer control register is organized as follows:
0286  *
0287  *    D0 - Enable
0288  *          1 = enable counting
0289  *          0 = hold scaler and counter
0290  *
0291  *    D1 - Counter Reload
0292  *          1 = reload counter at zero and restart
0293  *          0 = stop counter at zero
0294  *
0295  *    D2 - Counter Load
0296  *          1 = load counter with preset value
0297  *          0 = no function
0298  *
0299  */
0300
0301 #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
0302 #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
0303
0304 #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
0305
0306 #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
0307 #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
0308
0309 #define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
0310 #define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
0311
0312 #define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
0313 #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
0314
0315 /* Load 32-bit word by forcing a cache-miss */
0316 static inline unsigned int leon_r32_no_cache(uintptr_t addr)
0317 {
0318   unsigned int tmp;
0319   __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
0320   return tmp;
0321 }
0322
0323 /* Let user override which on-chip APBUART will be debug UART
0324  * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1...
0325  * 1 = APBUART[0]
0326  * 2 = APBUART[1]
0327  * 3 = APBUART[2]
0328  * ...
0329  */
0330 extern int syscon_uart_index;
0331
0332 #if !defined(LEON3_APBUART_BASE)
0333 /* Let user override which on-chip APBUART will be debug UART
0334  * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1...
0335  * 1 = APBUART[0]
0336  * 2 = APBUART[1]
0337  * 3 = APBUART[2]
0338  * ...
0339  */
0340 extern int leon3_debug_uart_index;
0341 #endif
0342
0343 #endif /* !ASM */
0344
0345 #ifdef __cplusplus
0346 }
0347 #endif
0348
0349 #endif /* !_INCLUDE_LEON_h */
0350 /* end of include file */
0351