include/bsp/gr740-thsens-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsGR740ThSens
0007  *
0008  * @brief This header file defines the GR740 Temperatur Sensor Controller
0009  *   register block interface.
0010  */
0011
0012 /*
0013  * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 /*
0038  * This file is part of the RTEMS quality process and was automatically
0039  * generated.  If you find something that needs to be fixed or
0040  * worded better please post a report or patch to an RTEMS mailing list
0041  * or raise a bug report:
0042  *
0043  * https://www.rtems.org/bugs.html
0044  *
0045  * For information on updating and regenerating please refer to the How-To
0046  * section in the Software Requirements Engineering chapter of the
0047  * RTEMS Software Engineering manual.  The manual is provided as a part of
0048  * a release.  For development sources please refer to the online
0049  * documentation at:
0050  *
0051  * https://docs.rtems.org
0052  */
0053
0054 /* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens-header */
0055
0056 #ifndef _BSP_GR740_THSENS_REGS_H
0057 #define _BSP_GR740_THSENS_REGS_H
0058
0059 #include <stdint.h>
0060
0061 #ifdef __cplusplus
0062 extern "C" {
0063 #endif
0064
0065 /* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens */
0066
0067 /**
0068  * @defgroup RTEMSBSPsGR740ThSens GR740 Temperatur Sensor Controller
0069  *
0070  * @ingroup RTEMSBSPsSPARCLEON3
0071  *
0072  * @brief This group contains the GR740 Temperatur Sensor Controller
0073  *   interfaces.
0074  *
0075  * @{
0076  */
0077
0078 /**
0079  * @defgroup RTEMSBSPsGR740ThSensCTRL Control register (CTRL)
0080  *
0081  * @brief This group contains register bit definitions.
0082  *
0083  * @{
0084  */
0085
0086 #define GR740_THSENS_CTRL_DIV_SHIFT 16
0087 #define GR740_THSENS_CTRL_DIV_MASK 0x3ff0000U
0088 #define GR740_THSENS_CTRL_DIV_GET( _reg ) \
0089   ( ( ( _reg ) & GR740_THSENS_CTRL_DIV_MASK ) >> \
0090     GR740_THSENS_CTRL_DIV_SHIFT )
0091 #define GR740_THSENS_CTRL_DIV_SET( _reg, _val ) \
0092   ( ( ( _reg ) & ~GR740_THSENS_CTRL_DIV_MASK ) | \
0093     ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \
0094       GR740_THSENS_CTRL_DIV_MASK ) )
0095 #define GR740_THSENS_CTRL_DIV( _val ) \
0096   ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \
0097     GR740_THSENS_CTRL_DIV_MASK )
0098
0099 #define GR740_THSENS_CTRL_ALEN 0x100U
0100
0101 #define GR740_THSENS_CTRL_PDN 0x80U
0102
0103 #define GR740_THSENS_CTRL_DCORRECT_SHIFT 2
0104 #define GR740_THSENS_CTRL_DCORRECT_MASK 0x7cU
0105 #define GR740_THSENS_CTRL_DCORRECT_GET( _reg ) \
0106   ( ( ( _reg ) & GR740_THSENS_CTRL_DCORRECT_MASK ) >> \
0107     GR740_THSENS_CTRL_DCORRECT_SHIFT )
0108 #define GR740_THSENS_CTRL_DCORRECT_SET( _reg, _val ) \
0109   ( ( ( _reg ) & ~GR740_THSENS_CTRL_DCORRECT_MASK ) | \
0110     ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \
0111       GR740_THSENS_CTRL_DCORRECT_MASK ) )
0112 #define GR740_THSENS_CTRL_DCORRECT( _val ) \
0113   ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \
0114     GR740_THSENS_CTRL_DCORRECT_MASK )
0115
0116 #define GR740_THSENS_CTRL_SRSTN 0x2U
0117
0118 #define GR740_THSENS_CTRL_CLKEN 0x1U
0119
0120 /** @} */
0121
0122 /**
0123  * @defgroup RTEMSBSPsGR740ThSensSTATUS Status register (STATUS)
0124  *
0125  * @brief This group contains register bit definitions.
0126  *
0127  * @{
0128  */
0129
0130 #define GR740_THSENS_STATUS_MAX_SHIFT 24
0131 #define GR740_THSENS_STATUS_MAX_MASK 0x7f000000U
0132 #define GR740_THSENS_STATUS_MAX_GET( _reg ) \
0133   ( ( ( _reg ) & GR740_THSENS_STATUS_MAX_MASK ) >> \
0134     GR740_THSENS_STATUS_MAX_SHIFT )
0135 #define GR740_THSENS_STATUS_MAX_SET( _reg, _val ) \
0136   ( ( ( _reg ) & ~GR740_THSENS_STATUS_MAX_MASK ) | \
0137     ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \
0138       GR740_THSENS_STATUS_MAX_MASK ) )
0139 #define GR740_THSENS_STATUS_MAX( _val ) \
0140   ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \
0141     GR740_THSENS_STATUS_MAX_MASK )
0142
0143 #define GR740_THSENS_STATUS_MIN_SHIFT 16
0144 #define GR740_THSENS_STATUS_MIN_MASK 0x7f0000U
0145 #define GR740_THSENS_STATUS_MIN_GET( _reg ) \
0146   ( ( ( _reg ) & GR740_THSENS_STATUS_MIN_MASK ) >> \
0147     GR740_THSENS_STATUS_MIN_SHIFT )
0148 #define GR740_THSENS_STATUS_MIN_SET( _reg, _val ) \
0149   ( ( ( _reg ) & ~GR740_THSENS_STATUS_MIN_MASK ) | \
0150     ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \
0151       GR740_THSENS_STATUS_MIN_MASK ) )
0152 #define GR740_THSENS_STATUS_MIN( _val ) \
0153   ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \
0154     GR740_THSENS_STATUS_MIN_MASK )
0155
0156 #define GR740_THSENS_STATUS_SCLK 0x8000U
0157
0158 #define GR740_THSENS_STATUS_WE 0x400U
0159
0160 #define GR740_THSENS_STATUS_UPD 0x200U
0161
0162 #define GR740_THSENS_STATUS_ALACT 0x100U
0163
0164 #define GR740_THSENS_STATUS_DATA_SHIFT 0
0165 #define GR740_THSENS_STATUS_DATA_MASK 0x7fU
0166 #define GR740_THSENS_STATUS_DATA_GET( _reg ) \
0167   ( ( ( _reg ) & GR740_THSENS_STATUS_DATA_MASK ) >> \
0168     GR740_THSENS_STATUS_DATA_SHIFT )
0169 #define GR740_THSENS_STATUS_DATA_SET( _reg, _val ) \
0170   ( ( ( _reg ) & ~GR740_THSENS_STATUS_DATA_MASK ) | \
0171     ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \
0172       GR740_THSENS_STATUS_DATA_MASK ) )
0173 #define GR740_THSENS_STATUS_DATA( _val ) \
0174   ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \
0175     GR740_THSENS_STATUS_DATA_MASK )
0176
0177 /** @} */
0178
0179 /**
0180  * @defgroup RTEMSBSPsGR740ThSensTHRES Threshold register (THRES)
0181  *
0182  * @brief This group contains register bit definitions.
0183  *
0184  * @{
0185  */
0186
0187 #define GR740_THSENS_THRES_THRES_SHIFT 0
0188 #define GR740_THSENS_THRES_THRES_MASK 0x7fU
0189 #define GR740_THSENS_THRES_THRES_GET( _reg ) \
0190   ( ( ( _reg ) & GR740_THSENS_THRES_THRES_MASK ) >> \
0191     GR740_THSENS_THRES_THRES_SHIFT )
0192 #define GR740_THSENS_THRES_THRES_SET( _reg, _val ) \
0193   ( ( ( _reg ) & ~GR740_THSENS_THRES_THRES_MASK ) | \
0194     ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \
0195       GR740_THSENS_THRES_THRES_MASK ) )
0196 #define GR740_THSENS_THRES_THRES( _val ) \
0197   ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \
0198     GR740_THSENS_THRES_THRES_MASK )
0199
0200 /** @} */
0201
0202 /**
0203  * @brief This structure defines the GR740 Temperatur Sensor Controller
0204  *   register block memory map.
0205  */
0206 typedef struct gr740_thsens {
0207   /**
0208    * @brief See @ref RTEMSBSPsGR740ThSensCTRL.
0209    */
0210   uint32_t ctrl;
0211
0212   /**
0213    * @brief See @ref RTEMSBSPsGR740ThSensSTATUS.
0214    */
0215   uint32_t status;
0216
0217   /**
0218    * @brief See @ref RTEMSBSPsGR740ThSensTHRES.
0219    */
0220   uint32_t thres;
0221 } gr740_thsens;
0222
0223 /** @} */
0224
0225 #ifdef __cplusplus
0226 }
0227 #endif
0228
0229 #endif /* _BSP_GR740_THSENS_REGS_H */