include/bsp/gr740-iopll-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsGR740IOPLL
0007  *
0008  * @brief This header file defines the GR740 I/O and PLL configuration register
0009  *   block interface.
0010  */
0011
0012 /*
0013  * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 /*
0038  * This file is part of the RTEMS quality process and was automatically
0039  * generated.  If you find something that needs to be fixed or
0040  * worded better please post a report or patch to an RTEMS mailing list
0041  * or raise a bug report:
0042  *
0043  * https://www.rtems.org/bugs.html
0044  *
0045  * For information on updating and regenerating please refer to the How-To
0046  * section in the Software Requirements Engineering chapter of the
0047  * RTEMS Software Engineering manual.  The manual is provided as a part of
0048  * a release.  For development sources please refer to the online
0049  * documentation at:
0050  *
0051  * https://docs.rtems.org
0052  */
0053
0054 /* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll-header */
0055
0056 #ifndef _BSP_GR740_IOPLL_REGS_H
0057 #define _BSP_GR740_IOPLL_REGS_H
0058
0059 #include <stdint.h>
0060
0061 #ifdef __cplusplus
0062 extern "C" {
0063 #endif
0064
0065 /* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll */
0066
0067 /**
0068  * @defgroup RTEMSBSPsGR740IOPLL GR740 I/0 and PLL Configuration
0069  *
0070  * @ingroup RTEMSBSPsSPARCLEON3
0071  *
0072  * @brief This group contains the GR740 I/0 and PLL Configuration interfaces.
0073  *
0074  * @{
0075  */
0076
0077 /**
0078  * @defgroup RTEMSBSPsGR740IOPLLFTMFUNC \
0079  *   FTMCTRL function enable register (FTMFUNC)
0080  *
0081  * @brief This group contains register bit definitions.
0082  *
0083  * @{
0084  */
0085
0086 #define GR740_IOPLL_FTMFUNC_FTMEN_SHIFT 0
0087 #define GR740_IOPLL_FTMFUNC_FTMEN_MASK 0x3fffffU
0088 #define GR740_IOPLL_FTMFUNC_FTMEN_GET( _reg ) \
0089   ( ( ( _reg ) & GR740_IOPLL_FTMFUNC_FTMEN_MASK ) >> \
0090     GR740_IOPLL_FTMFUNC_FTMEN_SHIFT )
0091 #define GR740_IOPLL_FTMFUNC_FTMEN_SET( _reg, _val ) \
0092   ( ( ( _reg ) & ~GR740_IOPLL_FTMFUNC_FTMEN_MASK ) | \
0093     ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
0094       GR740_IOPLL_FTMFUNC_FTMEN_MASK ) )
0095 #define GR740_IOPLL_FTMFUNC_FTMEN( _val ) \
0096   ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \
0097     GR740_IOPLL_FTMFUNC_FTMEN_MASK )
0098
0099 /** @} */
0100
0101 /**
0102  * @defgroup RTEMSBSPsGR740IOPLLALTFUNC \
0103  *   Alternative function enable register (ALTFUNC)
0104  *
0105  * @brief This group contains register bit definitions.
0106  *
0107  * @{
0108  */
0109
0110 #define GR740_IOPLL_ALTFUNC_ALTEN_SHIFT 0
0111 #define GR740_IOPLL_ALTFUNC_ALTEN_MASK 0x3fffffU
0112 #define GR740_IOPLL_ALTFUNC_ALTEN_GET( _reg ) \
0113   ( ( ( _reg ) & GR740_IOPLL_ALTFUNC_ALTEN_MASK ) >> \
0114     GR740_IOPLL_ALTFUNC_ALTEN_SHIFT )
0115 #define GR740_IOPLL_ALTFUNC_ALTEN_SET( _reg, _val ) \
0116   ( ( ( _reg ) & ~GR740_IOPLL_ALTFUNC_ALTEN_MASK ) | \
0117     ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
0118       GR740_IOPLL_ALTFUNC_ALTEN_MASK ) )
0119 #define GR740_IOPLL_ALTFUNC_ALTEN( _val ) \
0120   ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \
0121     GR740_IOPLL_ALTFUNC_ALTEN_MASK )
0122
0123 /** @} */
0124
0125 /**
0126  * @defgroup RTEMSBSPsGR740IOPLLLVDSMCLK \
0127  *   LVDS and memory clock pad enable register (LVDSMCLK)
0128  *
0129  * @brief This group contains register bit definitions.
0130  *
0131  * @{
0132  */
0133
0134 #define GR740_IOPLL_LVDSMCLK_SMEM 0x20000U
0135
0136 #define GR740_IOPLL_LVDSMCLK_DMEM 0x10000U
0137
0138 #define GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT 0
0139 #define GR740_IOPLL_LVDSMCLK_SPWOE_MASK 0xffU
0140 #define GR740_IOPLL_LVDSMCLK_SPWOE_GET( _reg ) \
0141   ( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \
0142     GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT )
0143 #define GR740_IOPLL_LVDSMCLK_SPWOE_SET( _reg, _val ) \
0144   ( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \
0145     ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
0146       GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) )
0147 #define GR740_IOPLL_LVDSMCLK_SPWOE( _val ) \
0148   ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \
0149     GR740_IOPLL_LVDSMCLK_SPWOE_MASK )
0150
0151 /** @} */
0152
0153 /**
0154  * @defgroup RTEMSBSPsGR740IOPLLPLLNEWCFG \
0155  *   PLL new configuration register (PLLNEWCFG)
0156  *
0157  * @brief This group contains register bit definitions.
0158  *
0159  * @{
0160  */
0161
0162 #define GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27
0163 #define GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U
0164 #define GR740_IOPLL_PLLNEWCFG_SWTAG_GET( _reg ) \
0165   ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) >> \
0166     GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT )
0167 #define GR740_IOPLL_PLLNEWCFG_SWTAG_SET( _reg, _val ) \
0168   ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) | \
0169     ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
0170       GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) )
0171 #define GR740_IOPLL_PLLNEWCFG_SWTAG( _val ) \
0172   ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \
0173     GR740_IOPLL_PLLNEWCFG_SWTAG_MASK )
0174
0175 #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18
0176 #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U
0177 #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \
0178   ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) >> \
0179     GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT )
0180 #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \
0181   ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) | \
0182     ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
0183       GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) )
0184 #define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG( _val ) \
0185   ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \
0186     GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK )
0187
0188 #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9
0189 #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U
0190 #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \
0191   ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) >> \
0192     GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT )
0193 #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \
0194   ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) | \
0195     ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
0196       GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) )
0197 #define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG( _val ) \
0198   ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \
0199     GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK )
0200
0201 #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0
0202 #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU
0203 #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \
0204   ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) >> \
0205     GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT )
0206 #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \
0207   ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) | \
0208     ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
0209       GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) )
0210 #define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG( _val ) \
0211   ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \
0212     GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK )
0213
0214 /** @} */
0215
0216 /**
0217  * @defgroup RTEMSBSPsGR740IOPLLPLLRECFG \
0218  *   PLL reconfigure command register (PLLRECFG)
0219  *
0220  * @brief This group contains register bit definitions.
0221  *
0222  * @{
0223  */
0224
0225 #define GR740_IOPLL_PLLRECFG_RECONF_SHIFT 0
0226 #define GR740_IOPLL_PLLRECFG_RECONF_MASK 0x7U
0227 #define GR740_IOPLL_PLLRECFG_RECONF_GET( _reg ) \
0228   ( ( ( _reg ) & GR740_IOPLL_PLLRECFG_RECONF_MASK ) >> \
0229     GR740_IOPLL_PLLRECFG_RECONF_SHIFT )
0230 #define GR740_IOPLL_PLLRECFG_RECONF_SET( _reg, _val ) \
0231   ( ( ( _reg ) & ~GR740_IOPLL_PLLRECFG_RECONF_MASK ) | \
0232     ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
0233       GR740_IOPLL_PLLRECFG_RECONF_MASK ) )
0234 #define GR740_IOPLL_PLLRECFG_RECONF( _val ) \
0235   ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \
0236     GR740_IOPLL_PLLRECFG_RECONF_MASK )
0237
0238 /** @} */
0239
0240 /**
0241  * @defgroup RTEMSBSPsGR740IOPLLPLLCURCFG \
0242  *   PLL current configuration register (PLLCURCFG)
0243  *
0244  * @brief This group contains register bit definitions.
0245  *
0246  * @{
0247  */
0248
0249 #define GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT 27
0250 #define GR740_IOPLL_PLLCURCFG_SWTAG_MASK 0x18000000U
0251 #define GR740_IOPLL_PLLCURCFG_SWTAG_GET( _reg ) \
0252   ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) >> \
0253     GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT )
0254 #define GR740_IOPLL_PLLCURCFG_SWTAG_SET( _reg, _val ) \
0255   ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) | \
0256     ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
0257       GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) )
0258 #define GR740_IOPLL_PLLCURCFG_SWTAG( _val ) \
0259   ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \
0260     GR740_IOPLL_PLLCURCFG_SWTAG_MASK )
0261
0262 #define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT 18
0263 #define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U
0264 #define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_GET( _reg ) \
0265   ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) >> \
0266     GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT )
0267 #define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \
0268   ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) | \
0269     ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
0270       GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) )
0271 #define GR740_IOPLL_PLLCURCFG_SPWPLLCFG( _val ) \
0272   ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \
0273     GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK )
0274
0275 #define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT 9
0276 #define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U
0277 #define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_GET( _reg ) \
0278   ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) >> \
0279     GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT )
0280 #define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \
0281   ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) | \
0282     ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
0283       GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) )
0284 #define GR740_IOPLL_PLLCURCFG_MEMPLLCFG( _val ) \
0285   ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \
0286     GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK )
0287
0288 #define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT 0
0289 #define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU
0290 #define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_GET( _reg ) \
0291   ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) >> \
0292     GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT )
0293 #define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \
0294   ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) | \
0295     ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
0296       GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) )
0297 #define GR740_IOPLL_PLLCURCFG_SYSPLLCFG( _val ) \
0298   ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \
0299     GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK )
0300
0301 /** @} */
0302
0303 /**
0304  * @defgroup RTEMSBSPsGR740IOPLLDRVSTR1 \
0305  *   Drive strength configuration register 1 (DRVSTR1)
0306  *
0307  * @brief This group contains register bit definitions.
0308  *
0309  * @{
0310  */
0311
0312 #define GR740_IOPLL_DRVSTR1_S9_SHIFT 18
0313 #define GR740_IOPLL_DRVSTR1_S9_MASK 0xc0000U
0314 #define GR740_IOPLL_DRVSTR1_S9_GET( _reg ) \
0315   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \
0316     GR740_IOPLL_DRVSTR1_S9_SHIFT )
0317 #define GR740_IOPLL_DRVSTR1_S9_SET( _reg, _val ) \
0318   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \
0319     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
0320       GR740_IOPLL_DRVSTR1_S9_MASK ) )
0321 #define GR740_IOPLL_DRVSTR1_S9( _val ) \
0322   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \
0323     GR740_IOPLL_DRVSTR1_S9_MASK )
0324
0325 #define GR740_IOPLL_DRVSTR1_S8_SHIFT 16
0326 #define GR740_IOPLL_DRVSTR1_S8_MASK 0x30000U
0327 #define GR740_IOPLL_DRVSTR1_S8_GET( _reg ) \
0328   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \
0329     GR740_IOPLL_DRVSTR1_S8_SHIFT )
0330 #define GR740_IOPLL_DRVSTR1_S8_SET( _reg, _val ) \
0331   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \
0332     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
0333       GR740_IOPLL_DRVSTR1_S8_MASK ) )
0334 #define GR740_IOPLL_DRVSTR1_S8( _val ) \
0335   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \
0336     GR740_IOPLL_DRVSTR1_S8_MASK )
0337
0338 #define GR740_IOPLL_DRVSTR1_S7_SHIFT 14
0339 #define GR740_IOPLL_DRVSTR1_S7_MASK 0xc000U
0340 #define GR740_IOPLL_DRVSTR1_S7_GET( _reg ) \
0341   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \
0342     GR740_IOPLL_DRVSTR1_S7_SHIFT )
0343 #define GR740_IOPLL_DRVSTR1_S7_SET( _reg, _val ) \
0344   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \
0345     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
0346       GR740_IOPLL_DRVSTR1_S7_MASK ) )
0347 #define GR740_IOPLL_DRVSTR1_S7( _val ) \
0348   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \
0349     GR740_IOPLL_DRVSTR1_S7_MASK )
0350
0351 #define GR740_IOPLL_DRVSTR1_S6_SHIFT 12
0352 #define GR740_IOPLL_DRVSTR1_S6_MASK 0x3000U
0353 #define GR740_IOPLL_DRVSTR1_S6_GET( _reg ) \
0354   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \
0355     GR740_IOPLL_DRVSTR1_S6_SHIFT )
0356 #define GR740_IOPLL_DRVSTR1_S6_SET( _reg, _val ) \
0357   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \
0358     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
0359       GR740_IOPLL_DRVSTR1_S6_MASK ) )
0360 #define GR740_IOPLL_DRVSTR1_S6( _val ) \
0361   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \
0362     GR740_IOPLL_DRVSTR1_S6_MASK )
0363
0364 #define GR740_IOPLL_DRVSTR1_S5_SHIFT 10
0365 #define GR740_IOPLL_DRVSTR1_S5_MASK 0xc00U
0366 #define GR740_IOPLL_DRVSTR1_S5_GET( _reg ) \
0367   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \
0368     GR740_IOPLL_DRVSTR1_S5_SHIFT )
0369 #define GR740_IOPLL_DRVSTR1_S5_SET( _reg, _val ) \
0370   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \
0371     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
0372       GR740_IOPLL_DRVSTR1_S5_MASK ) )
0373 #define GR740_IOPLL_DRVSTR1_S5( _val ) \
0374   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \
0375     GR740_IOPLL_DRVSTR1_S5_MASK )
0376
0377 #define GR740_IOPLL_DRVSTR1_S4_SHIFT 8
0378 #define GR740_IOPLL_DRVSTR1_S4_MASK 0x300U
0379 #define GR740_IOPLL_DRVSTR1_S4_GET( _reg ) \
0380   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \
0381     GR740_IOPLL_DRVSTR1_S4_SHIFT )
0382 #define GR740_IOPLL_DRVSTR1_S4_SET( _reg, _val ) \
0383   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \
0384     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
0385       GR740_IOPLL_DRVSTR1_S4_MASK ) )
0386 #define GR740_IOPLL_DRVSTR1_S4( _val ) \
0387   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \
0388     GR740_IOPLL_DRVSTR1_S4_MASK )
0389
0390 #define GR740_IOPLL_DRVSTR1_S3_SHIFT 6
0391 #define GR740_IOPLL_DRVSTR1_S3_MASK 0xc0U
0392 #define GR740_IOPLL_DRVSTR1_S3_GET( _reg ) \
0393   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \
0394     GR740_IOPLL_DRVSTR1_S3_SHIFT )
0395 #define GR740_IOPLL_DRVSTR1_S3_SET( _reg, _val ) \
0396   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \
0397     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
0398       GR740_IOPLL_DRVSTR1_S3_MASK ) )
0399 #define GR740_IOPLL_DRVSTR1_S3( _val ) \
0400   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \
0401     GR740_IOPLL_DRVSTR1_S3_MASK )
0402
0403 #define GR740_IOPLL_DRVSTR1_S2_SHIFT 4
0404 #define GR740_IOPLL_DRVSTR1_S2_MASK 0x30U
0405 #define GR740_IOPLL_DRVSTR1_S2_GET( _reg ) \
0406   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \
0407     GR740_IOPLL_DRVSTR1_S2_SHIFT )
0408 #define GR740_IOPLL_DRVSTR1_S2_SET( _reg, _val ) \
0409   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \
0410     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
0411       GR740_IOPLL_DRVSTR1_S2_MASK ) )
0412 #define GR740_IOPLL_DRVSTR1_S2( _val ) \
0413   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \
0414     GR740_IOPLL_DRVSTR1_S2_MASK )
0415
0416 #define GR740_IOPLL_DRVSTR1_S1_SHIFT 2
0417 #define GR740_IOPLL_DRVSTR1_S1_MASK 0xcU
0418 #define GR740_IOPLL_DRVSTR1_S1_GET( _reg ) \
0419   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \
0420     GR740_IOPLL_DRVSTR1_S1_SHIFT )
0421 #define GR740_IOPLL_DRVSTR1_S1_SET( _reg, _val ) \
0422   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \
0423     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
0424       GR740_IOPLL_DRVSTR1_S1_MASK ) )
0425 #define GR740_IOPLL_DRVSTR1_S1( _val ) \
0426   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \
0427     GR740_IOPLL_DRVSTR1_S1_MASK )
0428
0429 #define GR740_IOPLL_DRVSTR1_S0_SHIFT 0
0430 #define GR740_IOPLL_DRVSTR1_S0_MASK 0x3U
0431 #define GR740_IOPLL_DRVSTR1_S0_GET( _reg ) \
0432   ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \
0433     GR740_IOPLL_DRVSTR1_S0_SHIFT )
0434 #define GR740_IOPLL_DRVSTR1_S0_SET( _reg, _val ) \
0435   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \
0436     ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
0437       GR740_IOPLL_DRVSTR1_S0_MASK ) )
0438 #define GR740_IOPLL_DRVSTR1_S0( _val ) \
0439   ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \
0440     GR740_IOPLL_DRVSTR1_S0_MASK )
0441
0442 /** @} */
0443
0444 /**
0445  * @defgroup RTEMSBSPsGR740IOPLLDRVSTR2 \
0446  *   Drive strength configuration register 2 (DRVSTR2)
0447  *
0448  * @brief This group contains register bit definitions.
0449  *
0450  * @{
0451  */
0452
0453 #define GR740_IOPLL_DRVSTR2_S19_SHIFT 18
0454 #define GR740_IOPLL_DRVSTR2_S19_MASK 0xc0000U
0455 #define GR740_IOPLL_DRVSTR2_S19_GET( _reg ) \
0456   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S19_MASK ) >> \
0457     GR740_IOPLL_DRVSTR2_S19_SHIFT )
0458 #define GR740_IOPLL_DRVSTR2_S19_SET( _reg, _val ) \
0459   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S19_MASK ) | \
0460     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
0461       GR740_IOPLL_DRVSTR2_S19_MASK ) )
0462 #define GR740_IOPLL_DRVSTR2_S19( _val ) \
0463   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \
0464     GR740_IOPLL_DRVSTR2_S19_MASK )
0465
0466 #define GR740_IOPLL_DRVSTR2_S18_SHIFT 16
0467 #define GR740_IOPLL_DRVSTR2_S18_MASK 0x30000U
0468 #define GR740_IOPLL_DRVSTR2_S18_GET( _reg ) \
0469   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S18_MASK ) >> \
0470     GR740_IOPLL_DRVSTR2_S18_SHIFT )
0471 #define GR740_IOPLL_DRVSTR2_S18_SET( _reg, _val ) \
0472   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S18_MASK ) | \
0473     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
0474       GR740_IOPLL_DRVSTR2_S18_MASK ) )
0475 #define GR740_IOPLL_DRVSTR2_S18( _val ) \
0476   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \
0477     GR740_IOPLL_DRVSTR2_S18_MASK )
0478
0479 #define GR740_IOPLL_DRVSTR2_S17_SHIFT 14
0480 #define GR740_IOPLL_DRVSTR2_S17_MASK 0xc000U
0481 #define GR740_IOPLL_DRVSTR2_S17_GET( _reg ) \
0482   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S17_MASK ) >> \
0483     GR740_IOPLL_DRVSTR2_S17_SHIFT )
0484 #define GR740_IOPLL_DRVSTR2_S17_SET( _reg, _val ) \
0485   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S17_MASK ) | \
0486     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
0487       GR740_IOPLL_DRVSTR2_S17_MASK ) )
0488 #define GR740_IOPLL_DRVSTR2_S17( _val ) \
0489   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \
0490     GR740_IOPLL_DRVSTR2_S17_MASK )
0491
0492 #define GR740_IOPLL_DRVSTR2_S16_SHIFT 12
0493 #define GR740_IOPLL_DRVSTR2_S16_MASK 0x3000U
0494 #define GR740_IOPLL_DRVSTR2_S16_GET( _reg ) \
0495   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S16_MASK ) >> \
0496     GR740_IOPLL_DRVSTR2_S16_SHIFT )
0497 #define GR740_IOPLL_DRVSTR2_S16_SET( _reg, _val ) \
0498   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S16_MASK ) | \
0499     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
0500       GR740_IOPLL_DRVSTR2_S16_MASK ) )
0501 #define GR740_IOPLL_DRVSTR2_S16( _val ) \
0502   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \
0503     GR740_IOPLL_DRVSTR2_S16_MASK )
0504
0505 #define GR740_IOPLL_DRVSTR2_S15_SHIFT 10
0506 #define GR740_IOPLL_DRVSTR2_S15_MASK 0xc00U
0507 #define GR740_IOPLL_DRVSTR2_S15_GET( _reg ) \
0508   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S15_MASK ) >> \
0509     GR740_IOPLL_DRVSTR2_S15_SHIFT )
0510 #define GR740_IOPLL_DRVSTR2_S15_SET( _reg, _val ) \
0511   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S15_MASK ) | \
0512     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
0513       GR740_IOPLL_DRVSTR2_S15_MASK ) )
0514 #define GR740_IOPLL_DRVSTR2_S15( _val ) \
0515   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \
0516     GR740_IOPLL_DRVSTR2_S15_MASK )
0517
0518 #define GR740_IOPLL_DRVSTR2_S14_SHIFT 8
0519 #define GR740_IOPLL_DRVSTR2_S14_MASK 0x300U
0520 #define GR740_IOPLL_DRVSTR2_S14_GET( _reg ) \
0521   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S14_MASK ) >> \
0522     GR740_IOPLL_DRVSTR2_S14_SHIFT )
0523 #define GR740_IOPLL_DRVSTR2_S14_SET( _reg, _val ) \
0524   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S14_MASK ) | \
0525     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
0526       GR740_IOPLL_DRVSTR2_S14_MASK ) )
0527 #define GR740_IOPLL_DRVSTR2_S14( _val ) \
0528   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \
0529     GR740_IOPLL_DRVSTR2_S14_MASK )
0530
0531 #define GR740_IOPLL_DRVSTR2_S13_SHIFT 6
0532 #define GR740_IOPLL_DRVSTR2_S13_MASK 0xc0U
0533 #define GR740_IOPLL_DRVSTR2_S13_GET( _reg ) \
0534   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S13_MASK ) >> \
0535     GR740_IOPLL_DRVSTR2_S13_SHIFT )
0536 #define GR740_IOPLL_DRVSTR2_S13_SET( _reg, _val ) \
0537   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S13_MASK ) | \
0538     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
0539       GR740_IOPLL_DRVSTR2_S13_MASK ) )
0540 #define GR740_IOPLL_DRVSTR2_S13( _val ) \
0541   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \
0542     GR740_IOPLL_DRVSTR2_S13_MASK )
0543
0544 #define GR740_IOPLL_DRVSTR2_S12_SHIFT 4
0545 #define GR740_IOPLL_DRVSTR2_S12_MASK 0x30U
0546 #define GR740_IOPLL_DRVSTR2_S12_GET( _reg ) \
0547   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S12_MASK ) >> \
0548     GR740_IOPLL_DRVSTR2_S12_SHIFT )
0549 #define GR740_IOPLL_DRVSTR2_S12_SET( _reg, _val ) \
0550   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S12_MASK ) | \
0551     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
0552       GR740_IOPLL_DRVSTR2_S12_MASK ) )
0553 #define GR740_IOPLL_DRVSTR2_S12( _val ) \
0554   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \
0555     GR740_IOPLL_DRVSTR2_S12_MASK )
0556
0557 #define GR740_IOPLL_DRVSTR2_S11_SHIFT 2
0558 #define GR740_IOPLL_DRVSTR2_S11_MASK 0xcU
0559 #define GR740_IOPLL_DRVSTR2_S11_GET( _reg ) \
0560   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S11_MASK ) >> \
0561     GR740_IOPLL_DRVSTR2_S11_SHIFT )
0562 #define GR740_IOPLL_DRVSTR2_S11_SET( _reg, _val ) \
0563   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S11_MASK ) | \
0564     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
0565       GR740_IOPLL_DRVSTR2_S11_MASK ) )
0566 #define GR740_IOPLL_DRVSTR2_S11( _val ) \
0567   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \
0568     GR740_IOPLL_DRVSTR2_S11_MASK )
0569
0570 #define GR740_IOPLL_DRVSTR2_S10_SHIFT 0
0571 #define GR740_IOPLL_DRVSTR2_S10_MASK 0x3U
0572 #define GR740_IOPLL_DRVSTR2_S10_GET( _reg ) \
0573   ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S10_MASK ) >> \
0574     GR740_IOPLL_DRVSTR2_S10_SHIFT )
0575 #define GR740_IOPLL_DRVSTR2_S10_SET( _reg, _val ) \
0576   ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S10_MASK ) | \
0577     ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
0578       GR740_IOPLL_DRVSTR2_S10_MASK ) )
0579 #define GR740_IOPLL_DRVSTR2_S10( _val ) \
0580   ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \
0581     GR740_IOPLL_DRVSTR2_S10_MASK )
0582
0583 /** @} */
0584
0585 /**
0586  * @defgroup RTEMSBSPsGR740IOPLLLOCKDOWN \
0587  *   Configuration lockdown register (LOCKDOWN)
0588  *
0589  * @brief This group contains register bit definitions.
0590  *
0591  * @{
0592  */
0593
0594 #define GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT 16
0595 #define GR740_IOPLL_LOCKDOWN_PERMANENT_MASK 0xff0000U
0596 #define GR740_IOPLL_LOCKDOWN_PERMANENT_GET( _reg ) \
0597   ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) >> \
0598     GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT )
0599 #define GR740_IOPLL_LOCKDOWN_PERMANENT_SET( _reg, _val ) \
0600   ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) | \
0601     ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
0602       GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) )
0603 #define GR740_IOPLL_LOCKDOWN_PERMANENT( _val ) \
0604   ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \
0605     GR740_IOPLL_LOCKDOWN_PERMANENT_MASK )
0606
0607 #define GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT 0
0608 #define GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK 0xffU
0609 #define GR740_IOPLL_LOCKDOWN_REVOCABLE_GET( _reg ) \
0610   ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) >> \
0611     GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT )
0612 #define GR740_IOPLL_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \
0613   ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) | \
0614     ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
0615       GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) )
0616 #define GR740_IOPLL_LOCKDOWN_REVOCABLE( _val ) \
0617   ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \
0618     GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK )
0619
0620 /** @} */
0621
0622 /**
0623  * @brief This structure defines the GR740 I/0 and PLL Configuration register
0624  *   block memory map.
0625  */
0626 typedef struct gr740_iopll {
0627   /**
0628    * @brief See @ref RTEMSBSPsGR740IOPLLFTMFUNC.
0629    */
0630   uint32_t ftmfunc;
0631
0632   /**
0633    * @brief See @ref RTEMSBSPsGR740IOPLLALTFUNC.
0634    */
0635   uint32_t altfunc;
0636
0637   /**
0638    * @brief See @ref RTEMSBSPsGR740IOPLLLVDSMCLK.
0639    */
0640   uint32_t lvdsmclk;
0641
0642   /**
0643    * @brief See @ref RTEMSBSPsGR740IOPLLPLLNEWCFG.
0644    */
0645   uint32_t pllnewcfg;
0646
0647   /**
0648    * @brief See @ref RTEMSBSPsGR740IOPLLPLLRECFG.
0649    */
0650   uint32_t pllrecfg;
0651
0652   /**
0653    * @brief See @ref RTEMSBSPsGR740IOPLLPLLCURCFG.
0654    */
0655   uint32_t pllcurcfg;
0656
0657   /**
0658    * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR1.
0659    */
0660   uint32_t drvstr1;
0661
0662   /**
0663    * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR2.
0664    */
0665   uint32_t drvstr2;
0666
0667   /**
0668    * @brief See @ref RTEMSBSPsGR740IOPLLLOCKDOWN.
0669    */
0670   uint32_t lockdown;
0671 } gr740_iopll;
0672
0673 /** @} */
0674
0675 #ifdef __cplusplus
0676 }
0677 #endif
0678
0679 #endif /* _BSP_GR740_IOPLL_REGS_H */