leon2/include/leon.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsSPARCLEON2
0007  *
0008  *  This include file contains information pertaining to the LEON-1.
0009  *  The LEON-1 is a custom SPARC V7 implementation.
0010  *  This CPU has a number of on-board peripherals and
0011  *  was developed by the European Space Agency to target space applications.
0012  *
0013  *  NOTE:  Other than where absolutely required, this version currently
0014  *         supports only the peripherals and bits used by the basic board
0015  *         support package. This includes at least significant pieces of
0016  *         the following items:
0017  *
0018  *           + UART Channels A and B
0019  *           + Real Time Clock
0020  *           + Memory Control Register
0021  *           + Interrupt Control
0022  *
0023  */
0024
0025 /*
0026  *  COPYRIGHT (c) 1989-1998.
0027  *  On-Line Applications Research Corporation (OAR).
0028  *
0029  * Redistribution and use in source and binary forms, with or without
0030  * modification, are permitted provided that the following conditions
0031  * are met:
0032  * 1. Redistributions of source code must retain the above copyright
0033  *    notice, this list of conditions and the following disclaimer.
0034  * 2. Redistributions in binary form must reproduce the above copyright
0035  *    notice, this list of conditions and the following disclaimer in the
0036  *    documentation and/or other materials provided with the distribution.
0037  *
0038  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0039  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0040  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0041  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0042  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0043  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0044  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0045  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0046  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0047  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0048  * POSSIBILITY OF SUCH DAMAGE.
0049  *
0050  *  Ported to LEON implementation of the SPARC by On-Line Applications
0051  *  Research Corporation (OAR) under contract to the European Space
0052  *  Agency (ESA).
0053  *
0054  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
0055  *  European Space Agency.
0056  */
0057
0058 #ifndef _INCLUDE_LEON_h
0059 #define _INCLUDE_LEON_h
0060
0061 #include <rtems/score/sparc.h>
0062
0063 #ifdef __cplusplus
0064 extern "C" {
0065 #endif
0066
0067 /*
0068  *  Interrupt Sources
0069  *
0070  *  The interrupt source numbers directly map to the trap type and to
0071  *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
0072  *  and the Interrupt Pending Registers.
0073  */
0074
0075 #define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR  1
0076 #define LEON_INTERRUPT_UART_2_RX_TX              2
0077 #define LEON_INTERRUPT_UART_1_RX_TX              3
0078 #define LEON_INTERRUPT_EXTERNAL_0                4
0079 #define LEON_INTERRUPT_EXTERNAL_1                5
0080 #define LEON_INTERRUPT_EXTERNAL_2                6
0081 #define LEON_INTERRUPT_EXTERNAL_3                7
0082 #define LEON_INTERRUPT_TIMER1                    8
0083 #define LEON_INTERRUPT_TIMER2                    9
0084 #define LEON_INTERRUPT_EMPTY1                    10
0085 #define LEON_INTERRUPT_EMPTY2                    11
0086 #define LEON_INTERRUPT_EMPTY3                    12
0087 #define LEON_INTERRUPT_EMPTY4                    13
0088 #define LEON_INTERRUPT_EMPTY5                    14
0089 #define LEON_INTERRUPT_EMPTY6                    15
0090
0091 #ifndef ASM
0092
0093 /*
0094  *  Trap Types for on-chip peripherals
0095  *
0096  *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
0097  *
0098  *  NOTE: The priority level for each source corresponds to the least
0099  *        significant nibble of the trap type.
0100  */
0101
0102 #define LEON_TRAP_TYPE( _source ) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source )
0103
0104 #define LEON_TRAP_SOURCE( _trap ) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap )
0105
0106 #define LEON_INT_TRAP( _trap ) SPARC_IS_INTERRUPT_TRAP( _trap )
0107
0108 /*
0109  *  Structure for LEON memory mapped registers.
0110  *
0111  *  Source: Section 6.1 - On-chip registers
0112  *
0113  *  NOTE:  There is only one of these structures per CPU, its base address
0114  *         is 0x80000000, and the variable LEON_REG is placed there by the
0115  *         linkcmds file.
0116  */
0117
0118 typedef struct {
0119   volatile unsigned int Memory_Config_1;
0120   volatile unsigned int Memory_Config_2;
0121   volatile unsigned int Edac_Control;
0122   volatile unsigned int Failed_Address;
0123   volatile unsigned int Memory_Status;
0124   volatile unsigned int Cache_Control;
0125   volatile unsigned int Power_Down;
0126   volatile unsigned int Write_Protection_1;
0127   volatile unsigned int Write_Protection_2;
0128   volatile unsigned int Leon_Configuration;
0129   volatile unsigned int dummy2;
0130   volatile unsigned int dummy3;
0131   volatile unsigned int dummy4;
0132   volatile unsigned int dummy5;
0133   volatile unsigned int dummy6;
0134   volatile unsigned int dummy7;
0135   volatile unsigned int Timer_Counter_1;
0136   volatile unsigned int Timer_Reload_1;
0137   volatile unsigned int Timer_Control_1;
0138   volatile unsigned int Watchdog;
0139   volatile unsigned int Timer_Counter_2;
0140   volatile unsigned int Timer_Reload_2;
0141   volatile unsigned int Timer_Control_2;
0142   volatile unsigned int dummy8;
0143   volatile unsigned int Scaler_Counter;
0144   volatile unsigned int Scaler_Reload;
0145   volatile unsigned int dummy9;
0146   volatile unsigned int dummy10;
0147   volatile unsigned int UART_Channel_1;
0148   volatile unsigned int UART_Status_1;
0149   volatile unsigned int UART_Control_1;
0150   volatile unsigned int UART_Scaler_1;
0151   volatile unsigned int UART_Channel_2;
0152   volatile unsigned int UART_Status_2;
0153   volatile unsigned int UART_Control_2;
0154   volatile unsigned int UART_Scaler_2;
0155   volatile unsigned int Interrupt_Mask;
0156   volatile unsigned int Interrupt_Pending;
0157   volatile unsigned int Interrupt_Force;
0158   volatile unsigned int Interrupt_Clear;
0159   volatile unsigned int PIO_Data;
0160   volatile unsigned int PIO_Direction;
0161   volatile unsigned int PIO_Interrupt;
0162 } LEON_Register_Map;
0163
0164 #endif
0165
0166 /*
0167  *  The following constants are intended to be used ONLY in assembly
0168  *  language files.
0169  *
0170  *  NOTE:  The intended style of usage is to load the address of LEON REGS
0171  *         into a register and then use these as displacements from
0172  *         that register.
0173  */
0174
0175 #ifdef ASM
0176
0177 #define  LEON_REG_MEMCFG1_OFFSET                                  0x00
0178 #define  LEON_REG_MEMCFG2_OFFSET                                  0x04
0179 #define  LEON_REG_EDACCTRL_OFFSET                                 0x08
0180 #define  LEON_REG_FAILADDR_OFFSET                                 0x0C
0181 #define  LEON_REG_MEMSTATUS_OFFSET                                0x10
0182 #define  LEON_REG_CACHECTRL_OFFSET                                0x14
0183 #define  LEON_REG_POWERDOWN_OFFSET                                0x18
0184 #define  LEON_REG_WRITEPROT1_OFFSET                               0x1C
0185 #define  LEON_REG_WRITEPROT2_OFFSET                               0x20
0186 #define  LEON_REG_LEONCONF_OFFSET                                 0x24
0187 #define  LEON_REG_UNIMPLEMENTED_2_OFFSET                          0x28
0188 #define  LEON_REG_UNIMPLEMENTED_3_OFFSET                          0x2C
0189 #define  LEON_REG_UNIMPLEMENTED_4_OFFSET                          0x30
0190 #define  LEON_REG_UNIMPLEMENTED_5_OFFSET                          0x34
0191 #define  LEON_REG_UNIMPLEMENTED_6_OFFSET                          0x38
0192 #define  LEON_REG_UNIMPLEMENTED_7_OFFSET                          0x3C
0193 #define  LEON_REG_TIMERCNT1_OFFSET                                0x40
0194 #define  LEON_REG_TIMERLOAD1_OFFSET                               0x44
0195 #define  LEON_REG_TIMERCTRL1_OFFSET                               0x48
0196 #define  LEON_REG_WDOG_OFFSET                                     0x4C
0197 #define  LEON_REG_TIMERCNT2_OFFSET                                0x50
0198 #define  LEON_REG_TIMERLOAD2_OFFSET                               0x54
0199 #define  LEON_REG_TIMERCTRL2_OFFSET                               0x58
0200 #define  LEON_REG_UNIMPLEMENTED_8_OFFSET                          0x5C
0201 #define  LEON_REG_SCALERCNT_OFFSET                                0x60
0202 #define  LEON_REG_SCALER_LOAD_OFFSET                              0x64
0203 #define  LEON_REG_UNIMPLEMENTED_9_OFFSET                          0x68
0204 #define  LEON_REG_UNIMPLEMENTED_10_OFFSET                         0x6C
0205 #define  LEON_REG_UARTDATA1_OFFSET                                0x70
0206 #define  LEON_REG_UARTSTATUS1_OFFSET                              0x74
0207 #define  LEON_REG_UARTCTRL1_OFFSET                                0x78
0208 #define  LEON_REG_UARTSCALER1_OFFSET                              0x7C
0209 #define  LEON_REG_UARTDATA2_OFFSET                                0x80
0210 #define  LEON_REG_UARTSTATUS2_OFFSET                              0x84
0211 #define  LEON_REG_UARTCTRL2_OFFSET                                0x88
0212 #define  LEON_REG_UARTSCALER2_OFFSET                              0x8C
0213 #define  LEON_REG_IRQMASK_OFFSET                                  0x90
0214 #define  LEON_REG_IRQPEND_OFFSET                                  0x94
0215 #define  LEON_REG_IRQFORCE_OFFSET                                 0x98
0216 #define  LEON_REG_IRQCLEAR_OFFSET                                 0x9C
0217 #define  LEON_REG_PIODATA_OFFSET                                  0xA0
0218 #define  LEON_REG_PIODIR_OFFSET                                   0xA4
0219 #define  LEON_REG_PIOIRQ_OFFSET                                   0xA8
0220 #define  LEON_REG_SIM_RAM_SIZE_OFFSET                             0xF4
0221 #define  LEON_REG_SIM_ROM_SIZE_OFFSET                             0xF8
0222
0223 #endif
0224
0225 /*
0226  *  The following defines the bits in Memory Configuration Register 1.
0227  */
0228
0229 #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
0230
0231 /*
0232  *  The following defines the bits in Memory Configuration Register 1.
0233  */
0234
0235 #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
0236
0237
0238 /*
0239  *  The following defines the bits in the Timer Control Register.
0240  */
0241
0242 #define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
0243                                               /* 0 = hold scalar and counter */
0244 #define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
0245                                               /* 0 = stop at 0 */
0246 #define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
0247                                               /* 0 = no function */
0248
0249 /*
0250  *  The following defines the bits in the UART Control Registers.
0251  *
0252  */
0253
0254 #define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
0255
0256 /*
0257  *  The following defines the bits in the LEON UART Status Registers.
0258  */
0259
0260 #define LEON_REG_UART_STATUS_CLR  0x00000000 /* Clear all status bits */
0261 #define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
0262 #define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
0263 #define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
0264 #define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
0265 #define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
0266 #define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
0267 #define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
0268 #define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
0269
0270
0271 /*
0272  *  The following defines the bits in the LEON UART Status Registers.
0273  */
0274
0275 #define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
0276 #define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
0277 #define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
0278 #define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
0279 #define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
0280 #define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
0281 #define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
0282 #define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
0283
0284 #ifndef ASM
0285
0286 /*
0287  *  This is used to manipulate the on-chip registers.
0288  *
0289  *  The following symbol must be defined in the linkcmds file and point
0290  *  to the correct location.
0291  */
0292
0293 extern LEON_Register_Map LEON_REG;
0294
0295 /*
0296  *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
0297  *  and the Interrupt Pending Registers.
0298  *
0299  *  NOTE: For operations which are not atomic, this code disables interrupts
0300  *        to guarantee there are no intervening accesses to the same register.
0301  *        The operations which read the register, modify the value and then
0302  *        store the result back are vulnerable.
0303  */
0304
0305 #define LEON_Clear_interrupt( _source ) \
0306   do { \
0307     LEON_REG.Interrupt_Clear = (1 << (_source)); \
0308   } while (0)
0309
0310 #define LEON_Force_interrupt( _source ) \
0311   do { \
0312     uint32_t _level; \
0313     \
0314     _level = sparc_disable_interrupts(); \
0315       LEON_REG.Interrupt_Force |= (1 << (_source)); \
0316     sparc_enable_interrupts( _level ); \
0317   } while (0)
0318
0319 #define LEON_Is_interrupt_pending( _source ) \
0320   (LEON_REG.Interrupt_Pending & (1 << (_source)))
0321
0322 #define LEON_Is_interrupt_masked( _source ) \
0323   (!(LEON_REG.Interrupt_Mask & (1 << (_source))))
0324
0325 #define LEON_Mask_interrupt( _source ) \
0326   do { \
0327     uint32_t _level; \
0328     \
0329     _level = sparc_disable_interrupts(); \
0330       LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
0331     sparc_enable_interrupts( _level ); \
0332   } while (0)
0333
0334 #define LEON_Unmask_interrupt( _source ) \
0335   do { \
0336     uint32_t _level; \
0337     \
0338     _level = sparc_disable_interrupts(); \
0339       LEON_REG.Interrupt_Mask |= (1 << (_source)); \
0340     sparc_enable_interrupts( _level ); \
0341   } while (0)
0342
0343 #define LEON_Disable_interrupt( _source, _previous ) \
0344   do { \
0345     uint32_t _level; \
0346     uint32_t _mask = 1 << (_source); \
0347     \
0348     _level = sparc_disable_interrupts(); \
0349       (_previous) = LEON_REG.Interrupt_Mask; \
0350       LEON_REG.Interrupt_Mask = _previous & ~_mask; \
0351     sparc_enable_interrupts( _level ); \
0352     (_previous) &= _mask; \
0353   } while (0)
0354
0355 #define LEON_Restore_interrupt( _source, _previous ) \
0356   do { \
0357     uint32_t _level; \
0358     uint32_t _mask = 1 << (_source); \
0359     \
0360     _level = sparc_disable_interrupts(); \
0361       LEON_REG.Interrupt_Mask = \
0362         (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
0363     sparc_enable_interrupts( _level ); \
0364   } while (0)
0365
0366 /* Make all SPARC BSPs have common macros for interrupt handling */
0367 #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
0368 #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
0369 #define BSP_Clear_forced_interrupt( _source ) \
0370   do { \
0371     uint32_t _level; \
0372     \
0373     _level = sparc_disable_interrupts(); \
0374       LEON_REG.Interrupt_Force &= ~(1 << (_source)); \
0375     sparc_enable_interrupts( _level ); \
0376   } while (0)
0377 #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
0378 #define BSP_Is_interrupt_forced(_source) \
0379   (LEON_REG.Interrupt_Force & (1 << (_source)))
0380 #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
0381 #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
0382 #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
0383 #define BSP_Disable_interrupt(_source, _previous) \
0384         LEON_Disable_interrupt(_source, _prev)
0385 #define BSP_Restore_interrupt(_source, _previous) \
0386         LEON_Restore_interrupt(_source, _previous)
0387
0388 /* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
0389 #define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
0390         BSP_Is_interrupt_masked(_source)
0391 #define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
0392         BSP_Unmask_interrupt(_source)
0393 #define BSP_Cpu_Mask_interrupt(_source, _cpu) \
0394         BSP_Mask_interrupt(_source)
0395 #define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
0396         BSP_Disable_interrupt(_source, _prev)
0397 #define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
0398         BSP_Cpu_Restore_interrupt(_source, _previous)
0399
0400 /*
0401  *  Each timer control register is organized as follows:
0402  *
0403  *    D0 - Enable
0404  *          1 = enable counting
0405  *          0 = hold scaler and counter
0406  *
0407  *    D1 - Counter Reload
0408  *          1 = reload counter at zero and restart
0409  *          0 = stop counter at zero
0410  *
0411  *    D2 - Counter Load
0412  *          1 = load counter with preset value
0413  *          0 = no function
0414  *
0415  */
0416
0417 #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
0418 #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
0419
0420 #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
0421
0422 #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
0423 #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
0424
0425 #define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
0426 #define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
0427
0428 #define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
0429 #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
0430
0431 /* Load 32-bit word by forcing a cache-miss */
0432 static inline unsigned int leon_r32_no_cache(uintptr_t addr)
0433 {
0434   unsigned int tmp;
0435   __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
0436   return tmp;
0437 }
0438
0439 #endif /* !ASM */
0440
0441 #ifdef __cplusplus
0442 }
0443 #endif
0444
0445 #endif /* !_INCLUDE_LEON_h */
0446